The Analysis of Warpage for Integrated Circuit Devices

Abstract

This paper deals with thin elongated packaging for large size silicon chips and its warpage caused by temperature changes during the packaging process. An integrated circuit device is composed of several materials with different properties of which differences in the thermal expansion coefficients of the materials pose the largest influence on the resulting product. In the course of IC encapsulation, as the product goes through numerous processes, temperatures will rise and fall and cause the composing materials to experience repeated thermal expansion and shrinkage. Since the material layers are under perfect adhesion, any two neighboring materials with different thermal expansion coefficients will be stressed from the temperature change causing the product to deform.

Current IC warpage analytical model research is based mainly on Dr. Suhir's theory of the compatibility conditions for the interfacial strains. The analytical model in Dr. Suhir's theory is constructed upon four layers of two-dimensional materials. There are two sections in the model: one is the section comprising the silicon chip and one is the section without the silicon chip. The latter section is only roughly simulated with a single homogenous material and is unable to correctly simulate the geometric shape of an actual encapsulation component. This paper extends Dr. Suhir's analytical model to possessing unlimited layers and consisting of many sections. Thus, it not only increases the completeness and correctness of the analysis results but also resolves the problem of accommodating models with different geometric shapes.