This paper presents a mixed analog/digital circuit design and simulation for an architecture called the augmented adaptive resonance theory-1 neural network (AART1-NN). The circuit is implemented based on the transconductance-mode approach and mixed analog/digital components, in which analog circuits are used to fully incorporate the parallel mechanism of the neural network, whereas digital circuits are used to provide a reduced circuit size as well as more precise multiplication operation. The AART1-NN circuit implemented is simulated using Pspice, and the results are in good agreement with those calculated numerically from the coupled nonlinear differential equations governing the AART1-NN.
G. Carpenter and S. Grossberg, "A massively parallel architecture for self-organizing neural pattern recognition machine,"Computer Vision, Graphics, and Image Process., vol. 37, pp. 54-115, 1987.
2.
S. Grossberg , "Nonlinear neural networks: Principles, mechanisms, and architecture,"Neural Networks, vol. 1, pp. 17-61,1988.
3.
T.P. Caudell , G.S. Smith, D. Wunsch, and R. Escobedo, "ART-1 neural networks applied to group technology,"Proc. of Int. Joint Conference on Neural Networks, Seattle, WA , 1991.
4.
S.V. Kamarthi , S.R. Kumara, F.T. Yu , and I. Ham, "Neural networks and their applications in component design data retrieval,"Journal of Intelligent Manufacturing, vol. 1, pp. 125-140, 1990.
5.
C.L. Chen and Q.W. Yan, "Design of an assembly planning system using unsupervised learning algorithm,"Proc. of Int. Joint Conference on Neural Networks , Baltimore, 1992.
6.
P. Gaudiano and S. Grossberg, "A self-regulating generator of sample and hold random training vectors,"Proc. of Int. Joint Conference on Neural Networks, Washington, D.C., 1990.
7.
M. Seibert and A.M. Waxman, "Learning aspect graph representations of 3D objects in a neural network,"Proc. of Int. Joint Conference on Neural Networks, Washington, D.C., 1990.
8.
J.C. Rajapakse , O.G. Jakubowicz, and R.S. Acharya, "A real time ART1 based vision system for distortion invariant recognition and autoassociation,"Proc. of Int.
9.
Joint Conference on Neural Networks, Washington, D.C., 1990.
10.
S.W. Tsay, N. El-Leithy, and R.W. Newcomb, "CMOS realization of a class of Hartline neural pools,"Proc. IEEE Int. Symp. Circuits and Systems, pp. 2417-2420, New Orleans, LA, May, 1990.
11.
R.D. Reed and R.L. Geiger, "A multiple-input OTA circuit for neural networks,"IEEE Transactions on Circuits and Systems, vol. 36, pp. 767-770, May 1989.
12.
B. Nabet , R.B. Darling, and R.B. Pinter, "Implementation of front-end processor neural networks,"Neural Networks , vol. 5, pp. 891-902,1992.
13.
S.W. Tsay and R.W. Newcomb, "VLSI implementation of ART1 memories,"IEEE Trans. on Neural Networks , vol. 2, pp. 214-221, March 1991.
14.
A. Rao, M.R. Walker, L.T. Clark, L.A. Akers, and R.O. Grondin, "VLSI implementation of neural network,"Neural Computation , vol. 2, pp. 35-43,1990.
15.
A. Rao, M.R. Walker, L.T. Clark, and L.A. Akers, "Integrated circuit emulation of ART1 networks,"Proc
16.
. First IEEE Conf. on Artificial Neural Networks, pp. 37-41, 1989.
17.
G.L. Heileman , M. Georgiopoulos and C. Abdallah, "A Dynamical Adaptive Resonance Architecture,"IEEE Transactions on Neural networks, to appear; also partially published in the Proceedings of the IJCNN, vol. 3, Singapore, November 1991, pp. 2658-2663.
18.
B. Linares-Barranco , E. Sanchez-Sinencio, A. Rodriguez, and J.L. Huertas, "A modular T-mode design approach for analog neural network hardware implementations,"IEEE J. Solid-St. Circuits, vol. 27, 1992.
19.
B. Linares-Barranco , E. Sanchez-Sinencio, A. Rodriguez, and J.L. Huertas, "A CMOS analog adaptive BAM with on-chip learning and weight refreshing,"IEEE Trans. Neural Network, vol. 3, p. 445, 1993.
20.
C.A. Mead, Analog VLSI and Neural Network Systems, Ch. 6, Addison Wesley, Boston, MA, 1989 .
21.
E. Kreyszig , Advanced Engineering Mathematics , 4th Ed., John Wiley & Sons, New York, 1979.
