Sage Journals: Discover world-class research

Abstract

A particularly challenging neural network application requiring high-speed and intensive image processing capability is target acquisition and discrimination. It requires spatio-temporal recognition of point and resolved targets at high speeds. A reconfigur able neural architecture may discriminate targets from clutter or classify targets once resolved. By mating a 64 x 64 pixel array infrared (IR) image sensor to a 3-D stack (cube) of 64 neural-net ICs along respective edges, every pixel would directly input to a neural network, thereby processing the infor-mation with full parallelism. Being mated to the infrared sensor array, the cube would operate at 90°K temperature with <250 nanosecond signal processing speed and a low power consumption of only -2 watts. For low power and compactness in hardware, the emphasis has been on parallelism and analog signal processing. A versatile reconfigurable circuit is presented that offers a variety of neural architectures: multilayer perceptron, template matching with winner-take-all (WTA) circuitry, and a new architecture of cascade backpropagation (CBP). Special designs of analog neuron and synapse implemented in VLSI are presented which bear out high speed response both at room and low temperatures with synapse-neuron signal propagation times of ∼100 ns. The CBP learning algorithm is illustrated by solving in simulation the nonlinear 6-bit parity problem. Results show that this algorithm is robust even with synaptic resolutions limited to 5 bits. Therefore, it is particularly suitable for hardware implementation.

Keywords

Neuroprocessor cascade back propagation analog VLSI 3-D stack

Get full access to this article

View all access options for this article.

References

See for example Proceedings of the IEEE International Conference on Neural Networks, Vol. I to VII, Orlando, FL., 1994 .

S.P. Eberhardt , T. Daud , D.A. Kerns , T.X. Brown , and A.P. Thakoor , "Competitive neural architecture for hardware solution to the assignment problem," Neural Networks , vol. 4, no. 4, pp. 431-442, 1991.

S.P. Eberhardt , R. Tawel , T. Brown , T. Daud , and A. Thakoor , "Analog VLSI neural networks: Implementation issues and examples in optimization and supervised learning," IEEE Trans. Industrial Electronics, vol. 39, no. 6, pp. 552-564, 1992.

T. Duong , S. Kemeny , M. Tran , T. Daud , and A. Thakoor , "Low power analog neurosynapse chips for a 3-D 'sugarcube' neuroprocessor ," Proceedings of the IEEE , International Conference on Neural Networks, vol. III, Orlando, pp. 1907-1911, 1994.

J.J. Hopfield , "The effectiveness of analogue 'neural network" hardware," Network, vol. 1, no. 1, pp. 27-40, 1990.

John Carson , "On-focal plane array feature extraction using a 3-D artificial neural network (3DANN)," Proc. SPIE, vol. 1541, Infrared Sensors:Detectors, Electronics, and Signal Processing , Ed: T.S.J. Jayadev, Part I: pp. 141-144, Part II: 227-231, 1991.

T. Duong , Private communication.

S.E. Fahlman and C. Lebiere , "The cascade correlation learning architecture," in: Advances in Neural Information Processing Systems II, Ed: D. Touretzky , pp 524-532, Morgan Kaufmann , San Mateo, 1990.

T.A. Duong , S.P. Eberhardt , T. Daud , and A. Thakoor , "Learning in neural networks: VLSI implementaticm strategies," In: Fuzzy Logic and Neural Network Handbook, Ed: C.H. Chen , McGraw-Hill, 1995 (To be published).

10.

T. Duong , S. Kemeny , M. Tran , T. Daud , and A. Thakoor , "High speed low power analog ASICs for a 3-D neuroprocessor," Proc. SPIE/IST vol. 2424, Feb. 4-10, San Jose, 1995. (To be published).

11.

A.M. Chen and R. Hecht-Neilson , "On the geometry of feedforward neural network weight spaces," Proceedings of the 2nd IEE International Conference on Artificial Neural Networks, pp. 1-4, IEE Press, London, 1991.

12.

P.W. Hollis , J.S. Harper , and J.J. Paulos , "The effects of precision constraints in a backpropagation learning network," Neural Computation , vol. 2, 363-373,1990.

13.

T. Duong , A.R. Stubberud , and T. Daud , "Cascade error projection learning algorithm," (under preparation).

14.

G. Strang , Linear Algebra and its Applications, 3rd. Ed. Harcourt Brace Jovanovich, San Diego , 1988.

15.

D.B. Parker , "Optimal algorithms for adaptive networks: second order backpropagation, second order direct propagation, and second order Hebbian learning," Proceedings of the IEEE Ist. International Conference on Neural Networks, vol. II, pp. 593-600, San Diego, CA, 1987.

16.

M. Hoehfeld and S. Fahlman , "Learning with limited numerical precision using the cascade correlation algorithm," IEEE Trans. Neural Networks, vol. 3, 602-611, 1992.

Analog 3-D Neuroprocessor for Fast Frame Focal Plane Image Processing

Abstract

Keywords

Get full access to this article

References