Systolic array simulation for quantification of speed/area parameters

Abstract

A comprehensive circuit simulation of a VLSI (Very Large Scale Integration) systolic array processor for band matrix triangula tion is developed. A systolic array structure is composed of sim ple, regularly connected processing elements configured to rap idly triangulate large, band form, linear equation systems. I/O circuit models are developed which provide operand demulti plexinglmultiplexing necessary to convert serial operand I/O, at the chip boundaries, to a parallel broadcasting of operands to/from the processing cells.

The complete layout of the model is a tessellated design of pro cessing elements and I/O modules which ideally will be fabri cated on a single chip. Fundamental design parameters which may be manipulated in the simulation include a scalable litho graphic linewidth, the number of bits per word and matrix bandwidth.

Comparisons are made of total propagation delay time and chip size versus matrix bandwidth. These results, in turn, lead to an assessment of the feasibility and advantages of this type of special- purpose VLSI computing structure.

Keywords

banded matrices matrix triangulation systolic arrays VLSI computing VLSI simulation

Get full access to this article

View all access options for this article.

References

Eidson, J.C. "Fast Electron-Beam Lithography." IEEE Spectrum 18 (July 1981), 24-28.

Hsu, W.C. ; Leung, Y.Y.J. ; and Shanblatt, M.A. "Simulating VLSI Systolic Array Structures for Fast Matrix Triangulation ." Proceedings 13th Annual Modeling and Simulation Conference. Pittsburgh, Pa. (April 1982 ), 507-511.

Hsu, W.C. ; Leung, Y.Y.J. ; and Shanblatt, M.A. "Comparison of Input/Output Structures for Single Chip VLSI Systolic Arrays." Proceedings 25th Midwest Symposium on Circuits and Systems. Houghton, Mich. (August 1982), 528-534.

Hwang, K. and Cheng. Y.H. "VLSI Computing Structures for Solving Large-Scale Linear System of Equations." Proceedings 1980 International Conference on Parallel Processing (August 1980), 65-112.

Keyes, R.W. "Physical Limits in Semiconductor Electronics." Science 195 (March 1977), 1230-1235.

Kung, H.T. "The Structure of Parallel Algorithms." Advances in Computers. Academic Press 19 (1980), 65-112.

Mead, C. and Conway, L. Introduction to VLSI Systems Addison-Wesley, Reading, Mass. (1980).

Shanblatt, M.A. ; Mickle, M.H. ; and Vogt, W.G. "Optimal Ordering Strategies for Load Flows on an Array Processor." Proceedings 1981 International Conference on Electrical Energy (April 1981), 78-81.