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Abstract

This paper presents a non-isolated single switch converter with high voltage gain. Its circuit topology is combined with coupled-inductor, clamp circuit, and voltage lift capacitor techniques. The proposed converter has several advantages: First, the circuit is controlled by only single pulse width modulation (PWM) for the power switch, which keeps the circuit simple. Secondly, the proposed converter is used as a clamping circuit,which let the energy of the leakage inductance can be circulated to the capacitor, so that the voltage spike on the active switch can be suppressed, and improves efficiency. This paper will introduce the principle of action, theoretical analysis, and experimental waveform in order. Finally, in the case of input voltage of 48 V, output voltage of 400 V, and output power of 1 kW, the performance of the proposed converter is verified. As a result, the maximum efficiency is up to 96.5% and full load efficiency is 92.3%.

Keywords

High voltage gain coupled-inductor clamp circuit power converter voltage-lift capacitor

Introduction

With the shortage of energy and forever rising oil prices, renewable energy research and green energy are becoming more and more important. These clean energies, comprising fuel cell (F.C.), wind energy, and photovoltaics (PV) can be applied as distributed generation (DG) systems. In a solar photovoltaic system, energy is generated by solar cells, and electricity is generated by converting DC to AC, so high-efficiency inverters must be used. However, inverters have some problems, such as high swithching losses, large output filter space, and many harmonics.^1,2 High step-up dc–dc converters can be used in these systems as interface converters to increase the output voltage. By connecting these converters to each PV panels, they can be controlled a novel high step-up dc–dc converter was presented. The proposed converter benefits from some advantages such as low-ripple input current, high voltage gain, zero current switching of the main switch, and low voltage stress of the main switch.³ A new method is proposed for a high-boost high efficiency converter with low swithing stress.^4,5 The another presented converter is based on the SEPIC converter. However, the converter voltage gain is improved by employing a coupled inductor and two voltage multipliers.⁶ Recently, DC–DC converters with high conversion ratio become popular as required in the front-end of the electrical grid supplied by environmental friendly sources of energy, or in hybrid/electric vehicles, or in data and telecommunication applications.⁷ The proposed coupled-inductor-based high-gain dc-dc converter features reduced input current ripple.⁸ The challenges in high step-up renewable energy applications are summarized to generate the next generation non-isolated high step-up DC/DC converters. The output voltage generated by the photovoltaic arrays, the fuel stacks, the super capacitors, or the battery sources is relatively low, even lower than 48 V. It should be boosted to a high voltage, such as 380 V for the full bridge inverter or 760 V for the half bridge inverter in the 220 V AC grid-connected power system^9,10 as shown in Figure 1.

Figure 1.

System architecture of green energy and charging station.

This paper mainly designs 48 V_DC/400 V_DC converters. Traditional boost converters cannot provide such high boost ratios. However, isolated converters can achieve higher voltage boost ratios through the transformer turns ratio, such as flyback converters, full-bridge converters, but isolated converters suffer high voltage spikes and high power consumption due to the leakage inductance of the transformer. In order to solve the shortcomings of traditional converters and improve conversion efficiency and voltage gain, this thesis combines switched capacitor technology, boost capacitor technology and capacitor-diode voltage multiplier technology^11–13 to achieve transformerless, high boost ratio, and high efficiency DC converter.^13.14

This paper proposes an integrated boost-flyback converter architecture (IBFC).^12,15,16 The converters using coupled inductors can achieve high boost gain by adjusting the turns ratio, but the coupled inductors can cause leakage energy and voltage spikes. In order to solve the above two problems. This paper uses non-dissipative snubber circuit and active clamp circuit, which not only absorbs the leakage inductance energy of the coupled inductor,^17–21 but also limits the leakage voltage and spike voltage stress of the active switch, thereby improving the circuit efficiency.²²

The circuit diagram of the proposed converter is shown in Figure 2. Input DC voltage Vi, power switch S₁, primary side winding N₁, secondary side winding N₂, and third side winding N₃ are winding coupling inductors, clamping capacitor C₁, clamping diode D₁, voltage-boost Capacitor C₂, rectifier diodes D₂ and D_o, output capacitor C_o, and output load resistance R_o. Base on the working principle, when the power switch S₁ is turned on, the capacitor C₂ is charged by the input power Vi, the clamp capacitor C₁, the secondary side winding N₂, and the third side winding N₃ are charged in series. During the time interval switch S₁ is off, the leakage inductance L_k₁ and the magnetizing inductance L_m charge the capacitor C₁. In addition, a part of the energy of the magnetizing inductor L_m is released through the secondary side winding N₂ and the third side winding N₃ of the coupled inductor. The energy of the DC power supply Vi, the excitation inductor L_m, the capacitor C₂, and the secondary side winding N₂ is charged to the output capacitor C_o and the load R_o.

Figure 2.

Proposed high step-up DC/DC converter.

Analysis of proposed high step-up DC/DC converter

Operation principle of the proposed converter in continuous conduction mode (CCM)

As shown in Figure 3, the converter operates in continuous current mode (CCM) and the waveform working principle of each point

Figure 3.

The waveform of each point of the converter in one cycle.

According to Figure 4(a)–(f) are the six processes of the converter in continuous current mode, which are described as follows:

Figure 4.

Current-flow path of the operating modes at CCM: (a) Mode I, (b) Mode II, (c) Mode III, (d) Mode IV, (e) Mode V, and (f) ModeVI.

Mode I [t₀ ≤ t ≤ t₁] : At t = t₀, switch S₁ is turned on. Diode D₁ and D₂ are turned off, and D_o is turned on. The current-flow path is shown in Figure 4(a). The voltage equation of the primary-side of coupled-inductor is that $V_{i} = V_{Lm} + V_{Lk 1}$ . At this time, V_N₂ generates an induced voltage, the primary-side coupled inductance i_Lk₁ increases, and the secondary current i_LK₂ decreases. When the current i_L₂ = 0, no current flows through the diode D_o. Since the current i_Lk₁ is equal to i_Lm + n₂·i_L2 at t = t₁, this operating mode ends.

Mode II [t₁ ≤ t ≤ t₂]: The current path is shown in Figure 4(b). During this time, the switch S₁ and the diode D₂ are turned on, the input power V_i charges the inductor L_m, and the diodes D₁ and D_o are not turned on. Meanwhile, on the secondary-side winding N₂ is connected in series with voltages V_i, V_C₁, and V_N₃ to charge capacitor C₂·_N2 + n₃·V_N3_. The output capacitor Co provides energy to the load Ro. When t = t₂, switch S₁ is non-conducting, and this operation mode II ends.

Mode III [t₂ ≤ t ≤ t₃]: The current path is shown in Figure 4(c). During this time, the switch S₁, diode D₁, and diode Do are turned off, and D₂ is turned on. The leakage inductance L_k1 and the inductance L_m charge the parasitic capacitor Cds of the switch S₁. The input voltage charges the capacitor C₂ through the V_C₁, V_N₃, D₂, and V_L₂ paths. Output capacitor C_o provides the energy to the load R_o. While the capacitor voltage V_C₁ is equal to V_i + V_ds at t = t₃, diode D₁ conducts and this operating mode is ended.

Mode IV [t₃ ≤ t ≤ t₄]: The current path is shown in Figure 4(d). The switch S₁ and the diode Do are not conducting, and the diode D₁ and the diode D₂ are conducting. The energy of the leakage inductance L_k₁ and the inductance L_m charges the capacitor C₁, so the leakage inductance energy is recovered. When time t = t₄, the secondary side current i_D₂ = 0, the diode D₂ is cut off, and the diode D_o is on.

Mode V [t₄ ≤ t ≤ t₅]: The current-flow path is shown in Figure 4(e). During this time, switch S₁ is turned off. Diodes D₁ and D_o are turned on, and D₂ is turned off. At t = t₄, the leakage inductance L_k₁ and magnetizing inductor L_m charge capacitor C₁. The voltage stress on the switch is limited. Also, a part of the energy of magnetizing inductor L_m is released via the secondary-side of coupled-inductor. Therefore, diode D_o is turned on and current is starting to increase. The secondary-side voltage V_N₂ is connected in series with voltages V_i, V_Lm, and V_C₂. The energies of DC-source V_i, L_m, C₂, and N₂ charge output capacitor C_o and load R_o. When V_N₂ is equal to n₂V_Lm at t = t₅, this operating mode is ended.

Mode VI [t₅ ≤ t ≤ t₆]: The current-flow path is shown in Figure 4(f). During this time, switch S₁ is still turned off. Diodes D_o is turned on, D₁ and D₂ are turned off. The energy of magnetic inductor is released by coupling-inductor. The energy of the DC-source V_i, V_C₂, and magnetizing energy of L_m provide energy to output capacitor C_o and load R_o. This mode is ended at t = t₆ during S₁ is turned on at the beginning of the next switching period.

Steady-state analysis of the proposed converter in continuous conduction mode (CCM)

In order to analyze the steady-state characteristics of the proposed converter under Continuous Conduction Mode (CCM), the following formulas ignore the leakage inductance, the Equivalent series inductance (ESL) of the inductor winding, and the Equivalent Series Resistance (ESR) of the capacitor; the capacitors C₁, C₂ and C_o are ideal capacitors, and the coupled inductor model is L_m, And the output voltage is a fixed voltage.

As shown in Figure 5(a), the equivalent circuit when the power switch S₁ is turned on, the voltage on the magnetizing inductance V_Lm is V_i. Current $Δ i_{Lm (on)}$ is represented as

Δ {i_{Lm}}_{(on)} = \frac{V_{i}}{L_{m}} \cdot D \cdot T_{S}, (0 \leq t \leq D T_{S})

(1)

Figure 5.

The equivalent circuit of the proposed converter at CCM operation: (a) switch S₁ turned on and (b) switch S₁ turned off.

The voltage on C₂ can be written as

V_{C 2} = V_{i} + V_{C 1} + V_{N 2} + V_{N 3}

(2)

Figure 5(b) is the equivalent circuit when the power switch S₁ is off. At this time, the voltage across V_Lm can be expressed as

V_{Lm} = V_{o} - V_{i} - V_{C 2} - V_{N 2}

(3)

And current $Δ i_{Lm (off)}$ is expressed as

Δ i_{Lm (off)} = \frac{V_{o} - V_{i} - V_{C 2} - V_{N 2}}{L_{m}} \cdot (1 - D) \cdot T_{s}, (D T_{S} \leq t \leq T_{S})

(4)

According to the volt-second balance theorem, the voltage of the inductor V_Lm is expressed as:

V_{Lm} = \frac{D}{1 - D} \cdot V_{i}

(5)

The voltage which across the second-side winding V_N₂ and third-side winding V_N₃ are expressed as follows

V_{N 2} = n_{2} \cdot V_{i}

(6)

V_{N 3} = n_{3} \cdot V_{i}

(7)

The voltage of the clamp capacitor C₁ can be denoted as

V_{C 1} = V_{Lm} = \frac{D}{1 - D} \cdot V_{i}

(8)

By using the volt-second balance principle, (1) and (4) the follows equation can be represented as

Δ i_{Lm (on)} = Δ i_{Lm (off)}

(9)

Substituting (5)–(8) into (9), the output voltage V_o can be derived as

\frac{V_{o}}{V_{i}} = \frac{(2 + n_{2} + n_{3}) - n_{3} \cdot D}{1 - D}

(10)

The circuit of the voltage gain and duty cycle of the coupled inductor at various turns ratios is shown in Figure 6. Compared with increasing the third-side winding N₃, increasing the secondary-side winding N₂ can obtain a higher voltage gain.

Figure 6.

The effect of different turns ratios on the voltage gain and duty cycle of the converter.

Effects of the ESRs on the semiconductor devices

Figure 7 shows the equivalent circuit including inductor copper inductances r_L₁, r_L₂, and r_L₃, on resistances of diode r_D₁, r_D₂, and r_D₃, and on resistance r_DS(on) of the main switch. The following conditions of the proposed converter are assumed in this analysis of the Model.

The main switch parasitic capacitor and the diode capacitor are excluded.

During the switch is turned on can be modeled a resistance r_DS(on), and during the switch turned off can be modeled an infinite resistance.

The diodes are modeled by the forward voltage V_D₁, V_D₂, and V_Do, and the forward resistances r_D₁, r_D₂, and r_Do. When the diodes are reversed-biased they can be modeled by an infinite resistance.

The effect of leakage inductances L_k₁, L_k₂, and L_k₃ are neglected.

Switching loss and ESRs of capacitors are neglected.

Assumed the magnetizing inductor is sufficiently large to ensure a small-ripple current approximation.

To consider DC components during the off period, the average current is I_L₁ = i_L_1(t), and the average current is I_L₂ = i_L_2(t).

The capacitors C₁, C₂, and C_o are assumed to be large enough and output voltage V_o is constant.

Figure 7.

Equivalent circuit with copper and semiconductor losses.

Based on the Kirchhoff’s voltage law (KVL) principle, during the switch S₁ is turned on as shown in Figure 8(a), the following equations can be represented as follow

V_{i} = V_{L 1 (on)} + i_{L 1} \cdot r_{L 1} + i_{DS} \cdot r_{DS}

(11)

V_{L 1 (on)} = V_{i} - i_{L 1} \cdot (r_{L 1} + r_{DS}) - i_{L 2} \cdot r_{DS}

(12)

V_{C 2} = V_{i} + V_{C 1} + V_{L 2 (on)} + V_{L 3 (on)} - i_{L 2} \cdot (r_{L 2} + r_{L 3} + r_{D 2}) - i_{DS} \cdot r_{DS} - V_{D 2}

(13)

where

i_{DS} = i_{L 1} + i_{D 1}

i_{L 1} = i_{D 1} + i_{L 2}

Figure 8.

Equivalent circuit: (a) switch turned on and (b) switch turned off.

The current of output capacitors C_O, C₁, and C₂ are given as follows:

{i_{C 1}}^{+} = - i_{L 2}

(14)

{i_{C 2}}^{+} = i_{L 2}

(15)

{i_{CO}}^{+} = - \frac{V_{O}}{R_{L}} = - i_{O}

(16)

During the main switch S₁ is turned off as shown in Figure 8(b), the following equations can be represented as follow

V_{C 1} = V_{L 1 (off)} - i_{L 1} \cdot r_{L 1} - i_{D 1} \cdot r_{D 1} - V_{D 1}

(17)

V_{O} = V_{CO} = V_{i} + V_{L 1 (off)} + V_{C 2} + n_{2} \cdot V_{L 1 (off)} - i_{L 1} \cdot r_{L 1} - i_{L 2} \cdot (r_{L 2} + r_{DO}) - V_{DO}

(18)

The current of C₁, C₂, and output capacitor C_O are givens as follow

{i_{C 1}}^{-} = i_{L 1} - i_{L 2}

(19)

{i_{C 2}}^{-} = - i_{L 2}

(20)

{i_{CO}}^{-} = i_{L 2} - i_{O}

(21)

Substituting (13) into (18), the inductor voltage V_L_1(off) is derived as

\begin{matrix} V_{L 1 (off)} = \frac{1}{2 + n_{2}} \cdot [V_{O} - V_{i} (2 + n_{2} + n_{3}) + (i_{L 1} \cdot (2 r_{L 1} + r_{DS})) + (i_{D 1} \cdot r_{D 1}) \\ + (i_{L 1} \cdot (r_{L 1} + r_{DS})) \cdot (a + b) + (i_{L 2} \cdot r_{DS}) \cdot (a + b) \\ + (i_{L 2} \cdot (r_{L 2} + r_{L 3} + r_{D 2} + r_{DS})) + (i_{L 2} \cdot (r_{L 2} + r_{Do})) \\ + V_{D 1} + V_{D 2} + V_{Do}] \end{matrix}

(22)

Based on the amp-second balance principle, from (14)–(16) and (19)–(21) can be rewritten as follows:

\int_{0}^{D T_{S}} {i_{C 1}}^{+} dt + \int_{D T_{S}}^{T_{S}} {i_{C 1}}^{-} dt = 0

(23)

\int_{0}^{D T_{S}} {i_{C 2}}^{+} dt + \int_{D T_{S}}^{T_{S}} {i_{C 2}}^{-} dt = 0

(24)

\int_{0}^{D T_{S}} {i_{Co}}^{+} dt + \int_{D T_{S}}^{T_{S}} {i_{Co}}^{-} dt = 0

(25)

According to (25), the current flow path the C_o can be presented as

- \frac{V_{O}}{R_{L}} \cdot D T_{S} + (i_{L 2} - \frac{V_{O}}{R_{L}}) \cdot (1 - D) T_{S} = 0

(26)

Form equation (26), the current i_L₂ is determined as

i_{L 2} = \frac{1}{1 - D} \cdot \frac{V_{O}}{R_{L}}

(27)

According to (23), the current flow path the C₁ can be presented as

- \frac{1}{1 - D} \cdot \frac{V_{O}}{R_{L}} \cdot D T_{S} + i_{C 1} \cdot (1 - D) T_{S} = 0

(28)

Form equation (28), the current i_D₁ is determined as

i_{D 1} = \frac{D}{{(1 - D)}^{2}} \cdot \frac{V_{O}}{R_{L}}

(29)

According to (27) and (29), the current flow path the i_L₁ can be derived as follows

i_{L 1} = i_{D 1} + i_{L 2}

(30)

i_{L 1} = \frac{1}{{(1 - D)}^{2}} \cdot \frac{V_{O}}{R_{L}}

(31)

From (27) and (31), i_L₁ can be rewritten as

i_{L 1} = \frac{1}{1 - D} \cdot i_{L 2}

(32)

Where in the steady state, the principle of volt-second balance can be given as equation:

\begin{matrix} [V_{i} - [i_{L 1} \cdot (r_{L 1} + r_{DS})] - (i_{L 2} \cdot r_{DS})] \cdot D T_{S} = \frac{1}{2 + n_{2}} \cdot \\ {V_{CO} - V_{i} (2 + n_{2} + n_{3}) + (i_{L 1} \cdot (2 r_{L 1} + r_{DS})) \\ + (i_{D 1} \cdot r_{D 1}) + (i_{L 1} \cdot (r_{L 1} + r_{DS})) \cdot (n_{2} + n_{3}) \\ + (i_{L 2} \cdot r_{DS}) \cdot (n_{2} + n_{3}) + (i_{L 2} \cdot (r_{L 2} + r_{L 3} + r_{D 2} + r_{DS})) \\ + (i_{L 2} \cdot (r_{L 2} + r_{Do})) + V_{D 1} + V_{D 2} + V_{Do}} \cdot (1 - D) T_{S} \end{matrix}

(33)

Where $n_{2} = \frac{N_{2}}{N_{1}}$ , $n_{3} = \frac{N_{3}}{N_{1}}$

Substituting (32) into (33), the equation can be rewritten as

\begin{matrix} V_{O} = (\frac{(2 + n_{2} + n_{3}) - n_{3} \cdot D}{1 - D}) \cdot V_{i} - (V_{D 1} + V_{D 2} + V_{Do}) \\ - [(2 + n_{2}) \cdot \frac{D}{1 - D} + (2 + n_{2} + n_{3})] \cdot i_{L 1} \cdot r_{L 1} \\ - 2 (1 - D) \cdot i_{L 1} \cdot r_{L 2} - (1 - D) \cdot i_{L 1} \cdot r_{L 3} \\ - [(2 + n_{2}) \cdot (\frac{D}{1 - D} + D) + (1 + n_{2} + n_{3}) \cdot (2 - D)] \cdot i_{L 1} \cdot r_{DS} \\ - [D \cdot r_{D 1} + (1 - D) \cdot (r_{D 2} + r_{Do})] \cdot i_{L 1} \end{matrix}

(34)

Substituting (31) into (34), the proposed converter output voltage V_O is derived as

\begin{matrix} V_{O} = (\frac{(2 + n_{2} + n_{3}) - n_{3} \cdot D}{1 - D}) \cdot V_{i} - V_{O} \\ \cdot {\frac{a}{{(1 - D)}^{3} \cdot R_{L}} + \frac{b}{{(1 - D)}^{2} \cdot R_{L}} + \frac{c}{(1 - D) \cdot R_{L}}} - \frac{d}{V_{i}} \end{matrix}

(35)

Where ${\begin{matrix} a = (2 + n_{2}) \cdot ((r_{L 1} + r_{DS}) \cdot D) \\ b = (2 + n_{2} + n_{3}) \cdot r_{L 1} + (2 + n_{2}) \cdot r_{DS} \cdot D + (1 + n_{2} + n_{3}) \cdot r_{DS} + r_{D 1} \cdot D \\ c = 2 r_{L 2} + r_{L 3} + (1 + n_{2} + n_{3}) \cdot r_{DS} + r_{D 2} + r_{Do} \\ d = (V_{D 1} + V_{D 2} + V_{Do}) \end{matrix}$

and $n_{2} = \frac{N_{2}}{N_{1}}$ , $n_{3} = \frac{N_{3}}{N_{1}}$ .

From equation (35), the voltage conversion ratio V_O/V_i is represented as follows:

\begin{matrix} \frac{V_{O}}{V_{i}} = \frac{(\frac{(2 + n_{2} + n_{3}) - n_{3} \cdot D}{1 - D}) \cdot (1 - \frac{1}{\frac{(2 + n_{2}) \cdot D}{1 - D} + (2 + n_{2} + n_{3})} \cdot \frac{d}{V_{i}})}{1 + [\frac{a}{{(1 - D)}^{3} \cdot R_{L}} + \frac{b}{{(1 - D)}^{2} \cdot R_{L}} + \frac{c}{(1 - D) \cdot R_{L}}]} \end{matrix}

(36)

The voltage gain and efficiency affected by different ESRs with coupled-inductor is shown in Figure 9. It can be seen that increase the equivalent series resistance r_L₁ is obtained lower voltage gain than increase the equivalent series resistance r_L₂ or r_L₃. The maximal voltage gain is constrained by the equivalent series resistances, and the efficiency will be decreased by the extreme duty ratio.

Figure 9.

Voltage gain versus duty ratio and efficiency versus duty ratio under different ESRs with coupled-inductor.

Neglecting the equivalent series resistance of the proposed converter, the ideal voltage gain can be expressed as

M_{CCM} = \frac{V_{O}}{V_{i}} = \frac{(2 + n_{2} + n_{3}) - n_{3} \cdot D}{1 - D}

(37)

According to (36), the equation can be reorganized and the equivalent circuit is shown in Figure 10 as follows

\begin{matrix} V_{i} \cdot ((2 + n_{2} + n_{3}) - n_{3} \cdot D) - V_{O} \cdot (1 - D) - i_{L 1} \cdot r_{L 1} \cdot a - i_{L 1} \cdot r_{L 2} \cdot b \\ - i_{L 1} \cdot r_{L 3} \cdot c - i_{L 1} \cdot r_{DS} \cdot d - i_{L 1} \cdot r_{DX} - V_{DX} = 0 \end{matrix}

(38)

Where ${\begin{matrix} a = (2 + 3 \cdot n_{2} + n_{3}) - D \cdot (n_{2} + n_{3}) \\ b = 2 \cdot {(1 - D)}^{2} \\ c = {(1 - D)}^{2} \\ d = 2 \cdot (1 + n_{2} + n_{3}) + D \cdot (1 - n_{2} - 3 \cdot n_{3} - D) \end{matrix}$

and ${\begin{matrix} r_{DX} = r_{D 1} \cdot D (1 - D) + (r_{D 2} + r_{DO}) {(1 - D)}^{2} \\ V_{DX} = (V_{D 1} + V_{D 2} + V_{DO}) (1 - D) \end{matrix}$

Figure 10.

Equivalent circuit corresponding to equation (54).

The input power and output power of the converter can be calculated as shown in equation (39) and (40), respectively.

P_{in} = ((2 + n_{2} + n_{3}) - n_{3} \cdot D) V_{i} \cdot i_{L 1}

(39)

P_{out} = (1 - D) V_{O} \cdot i_{L 1}

(40)

η = \frac{P_{out}}{P_{in}}

(41)

According to the equations (39)–(41), the converter efficiency can be derived as follows

η = \frac{1 - (\frac{(2 + n_{2} + n_{3}) - n_{3} \cdot D}{1 - D}) \cdot \frac{d}{V_{i}}}{1 + [\frac{a}{{(1 - D)}^{3} \cdot R_{L}} + \frac{b}{{(1 - D)}^{2} \cdot R_{L}} + \frac{c}{(1 - D) \cdot R_{L}}]}

(42)

and $n_{2} = \frac{N_{2}}{N_{1}}$ , $n_{3} = \frac{N_{3}}{N_{1}}$ .

From equation (42) shows that the efficiency is affected by the equivalent series resistance. Figure 11 shows the voltage gain and efficiency affected by various turns ratios and ESRs.

Figure 11.

The efficiency versus duty ratio under various turn ratios and ESRs.

To analysis of the effect on leakage inductance and winding resistance leads to the current waveform being exponential functions at the off period of the switching cycle, as shown in Figure 12.

Figure 12.

The equivalent circuit during switch S₁ turned off period.

The maximal magnetizing current at ton as follow

i_{Lm (peak) (on)} = (\frac{V_{i}}{L_{m} + L_{k 1}} + \frac{V_{i}}{L_{k 2} + L_{k 3}}) \cdot t_{on} + t_{i} (0)

(43)

The magnetizing current during switch S₁ in turned off can be given as follows:

i_{Lm} = i_{Lk 1} + n_{2} \cdot i_{Do}

(44)

i_{Lk 1} = i_{D 1} + i_{Do}

(45)

Substituting equations (45) into (44) derived as

i_{Lm} = i_{D 1} + (1 + n_{2}) \cdot i_{Do}

(46)

During switch S₁ in turned off, the voltage across the magnetizing inductor V_Lm and leakage inductance L_k₁ can be expressed as

V_{Lm} = L_{m} \frac{d}{dt} i_{Lm} = L_{m} \frac{d}{dt} (i_{D 1} + (1 + n_{2}) \cdot i_{Do})

\Rightarrow V_{Lm} = L_{m} \frac{d}{dt} i_{D 1} + (1 + n_{2}) \cdot L_{m} \frac{d}{dt} i_{Do}

(47)

V_{Lk 1} = L_{k 1} \frac{d}{dt} (i_{D 1} + i_{Do})

(48)

The voltage across the secondary winding V_L₂ and the leakage inductance L_k₂ can be expressed as

V_{L 2} = n_{2} \cdot L_{m} = n_{2} \cdot L_{m} \frac{d}{dt} (i_{D 1} + i_{Do} (1 + n_{2}))

(49)

\Rightarrow V_{L 2} = n_{2} \cdot L_{m} \frac{d}{dt} i_{D 1} + (n_{2} + {n_{2}}^{2}) \cdot L_{m} \frac{d}{dt} i_{Do}

(50)

V_{Lk 2} = L_{k 2} \frac{d}{dt} i_{Do}

(51)

Based on the Kirchhoff’s voltage law (KVL) to find the inductor voltage during the switch S₁ is turned off period of each cycle is represented as follow:

V_{o} = V_{i} + V_{Lm} + V_{Lk 1} + V_{C 2} + V_{L 2} + V_{Lk 2} - (i_{D 1} + i_{Do}) \cdot r_{L 1} - i_{Do} \cdot r_{L 2}

(52)

Then

V_{o} - V_{i} - V_{C 2} = V_{Lm} + V_{Lk 1} + V_{L 2} + V_{Lk 2} - (i_{D 1} + i_{Do}) \cdot r_{L 1} - i_{Do} \cdot r_{L 2}

(53)

Therefore

\begin{matrix} V_{o} - V_{i} - V_{C 2} = (L_{m} + L_{k 1} + n_{2} \cdot Lm) \cdot \frac{d}{dt} i_{D 1} \\ + ((1 + n_{2}) L_{m} + L_{k 1} + (n_{2} + {n_{2}}^{2}) \cdot Lm) \cdot \frac{d}{dt} i_{Do} - (i_{D 1} + i_{Do}) \cdot r_{L 1} - i_{Do} \cdot r_{L 2} \end{matrix}

(54)

The other loop of current id1 flow through D₁ to charge the clamped capacitor C₁, the equation can be represented as:

V_{C 1} = V_{Lm} + V_{Lk 1} - (i_{D 1} + i_{Do}) \cdot r_{L 1}

\Rightarrow V_{C 1} = (L_{m} + L_{k 1}) \frac{d}{dt} i_{D 1} + ((1 + n_{2}) \cdot L_{m} + L_{k 1}) V_{Lm} \frac{d}{dt} i_{Do} - (i_{D 1} + i_{Do}) \cdot r_{L 1}

(55)

According equations (54) and (55) in matrix form can be rewritten as

\begin{matrix} [\begin{matrix} V_{O} - V_{i} - V_{C 2} \\ V_{C 1} \end{matrix}] = [\begin{matrix} i_{d 1} (t) \\ i_{do} (t) \end{matrix}] \cdot \\ [\begin{matrix} (L_{m} + L_{K 1} + n_{2} \cdot L_{m}) \cdot D - r_{L 1} ((1 + n_{2}) \cdot L_{m} + L_{K 1} + (n_{2} + {n_{2}}^{2}) \cdot L_{m}) \cdot D - (r_{L 1} + r_{L 2}) \\ (L_{m} + L_{K 1}) \cdot D - r_{L 1} ((1 + n_{2}) \cdot L_{m} + L_{K 1}) \cdot D - r_{L 1} \end{matrix}] D \in \frac{d}{dt} \end{matrix}

(56)

From equation (56), by using the Kramer Law to solving of the i_D₁ and i_Do can be derived as follow:

\begin{matrix} i_{D 1} = \frac{- K_{1} \cdot r_{L 1} + K_{2} \cdot (r_{L 1} + r_{L 2})}{α \cdot D^{2} - β \cdot D - γ} = \frac{- K_{1} \cdot \frac{r_{L 1}}{α} + K_{2} \cdot \frac{(r_{L 1} + r_{L 2})}{α}}{D^{2} - \frac{β}{α} \cdot D - \frac{γ}{α}} \\ = \frac{- K_{1} \cdot \frac{r_{L 1}}{α} + K_{2} \cdot \frac{(r_{L 1} + r_{L 2})}{α}}{(D - P_{1}) \cdot (D + P_{2})} \\ = c_{1} \cdot e^{P_{1} t} + c_{2} \cdot e^{P_{2} t} + (\frac{(K_{1} - K_{2})}{r_{L 2}} - \frac{K_{2}}{r_{L 1}}) \end{matrix}

(57)

\begin{matrix} i_{Do} = \frac{- K_{1} \cdot r_{L 1} + K_{2} \cdot r_{L 1}}{α \cdot D^{2} - β \cdot D - γ} = \frac{- K_{1} \cdot \frac{r_{L 1}}{α} + K_{2} \cdot \frac{r_{L 1}}{α}}{D^{2} - \frac{β}{α} \cdot D - \frac{γ}{α}} = \frac{- K_{1} \cdot \frac{r_{L 1}}{α} + K_{2} \cdot \frac{r_{L 1}}{α}}{(D - P_{1}) \cdot (D + P_{2})} \\ = d_{1} \cdot e^{P_{1} t} + d_{2} \cdot e^{P_{2} t} - \frac{(K_{1} - K_{2})}{r_{L 2}} \end{matrix}

(58)

Where: ${\begin{matrix} α = n_{2} \cdot L_{m} \cdot L_{k 1} - ({n_{2}}^{2} + n_{2}) \cdot L_{m} \cdot L_{k 1} \\ β = - {r_{L 1} \cdot (n_{2} \cdot L_{m} - ({n_{2}}^{2} + n_{2}) \cdot L_{m}) + r_{L 2} \cdot (L_{m} + L_{k 1})} \\ γ = - r_{L 1} \cdot r_{L 2} \end{matrix}$

and ${\begin{matrix} P_{1} = \frac{β + \sqrt{β^{2} + (4 \cdot α \cdot γ)}}{2 α} \\ P_{2} = \frac{β - \sqrt{β^{2} + (4 \cdot α \cdot γ)}}{2 α} \end{matrix}$

and ${\begin{matrix} K_{1} = V_{O} + V_{i} - V_{C 2} \\ K_{2} = V_{C 1} \end{matrix}$

and $n_{2} = \frac{N_{2}}{N_{1}}$ , $n_{3} = \frac{N_{3}}{N_{1}}$ .

Substituting equations (57), (58) into (55) is obtained the following

c_{1} = \frac{r_{L 1} - ((1 + n_{2}) \cdot L_{m} + L_{k 1}) \cdot P_{1}}{(L_{m} + L_{k 1}) \cdot P_{1} - r_{L 1}} \cdot d_{1}

(59)

c_{2} = \frac{r_{L 1} - ((1 + n_{2}) \cdot L_{m} + L_{k 1}) \cdot P_{2}}{(L_{m} + L_{k 1}) \cdot P_{2} - r_{L 1}} \cdot d_{2}

(60)

Substituting equations (59) and (60) into (57) and (58) given as

{\begin{matrix} i_{D 1} (t) = A_{1} \cdot d_{1} \cdot e^{P_{1} t} + A_{2} \cdot d_{2} \cdot e^{P_{2} t} + A_{3} \\ i_{Do} (t) = d_{1} \cdot e^{P_{1} t} + d_{2} \cdot e^{P_{2} t} + A_{4} \end{matrix}

(61)

Where: ${\begin{matrix} A_{1} = \frac{r_{L 1} - ((1 + n_{2}) \cdot L_{m} + L_{k 1}) \cdot P_{1}}{(L_{m} + L_{k 1}) \cdot P_{1} - r_{L 1}} \\ A_{2} = \frac{r_{L 1} - ((1 + n_{2}) \cdot L_{m} + L_{k 1}) \cdot P_{2}}{(L_{m} + L_{k 1}) \cdot P_{2} - r_{L 1}} \\ A_{3} = \frac{(K_{1} - K_{2})}{r_{L 2}} - \frac{K_{2}}{r_{L 1}} \\ A_{4} = - \frac{(K_{1} - K_{2})}{r_{L 2}} \end{matrix}$

From equation (61) the initial current of i_D₁ and i_Do are as follow respectively:

{\begin{matrix} i_{D 1} (0) = I_{P} = A_{1} \cdot d_{1} + A_{2} \cdot d_{2} + A_{3} \\ i_{Do} (0) = I_{S} = d_{1} + d_{2} + A_{4} \end{matrix}

(62)

By solving the equation (62) can be derived as follow:

d_{1} = \frac{[\begin{matrix} I_{P} - A_{3} A_{2} \\ I_{S} - A_{4} 1 \end{matrix}]}{A_{1} - A_{2}} = \frac{(I_{P} - A_{3}) - (I_{S} - A_{4}) \cdot A_{2}}{A_{1} - A_{2}}

(63)

d_{2} = \frac{[\begin{matrix} A_{1} I_{p} - A_{3} \\ 1 Is - A_{4} \end{matrix}]}{A_{1} - A_{2}} = \frac{(I_{S} - A_{4}) \cdot A_{1} - (I_{P} - A_{3})}{A_{1} - A_{2}}

(64)

From equation (56) that the ESRs are neglected, the off period current i_d₁ and ido can be derived as

\begin{matrix} i_{D_{1}} = \frac{(V_{O} - V_{i} - V_{C 2}) \cdot [(1 + n_{1}) L_{m} + L_{k 1}] - V_{C 1} [(1 + 2 \cdot n_{1} + {n_{1}}^{2}) L_{m} + L_{k 1}]}{{(L_{m} + L_{k 1} + a \cdot L_{m})}^{2} - (L_{m} + L_{k 1}) [(1 + 2 \cdot n_{1} + {n_{1}}^{2}) L_{m} + L_{k 1}]} \\ \cdot t + i_{D 1} (0) \end{matrix}

(65)

i_{Do} = \frac{V_{C 1} (L_{m} + L_{k 1} + a \cdot L_{m}) - (V_{O} - V_{i} - V_{C 2}) (L_{m} + L_{k 1})}{{(L_{m} + L_{k 1} + a \cdot L_{m})}^{2} - (L_{m} + L_{k 1}) [(1 + 2 \cdot n_{1} + {n_{1}}^{2}) L_{m} + L_{k 1}]} \cdot t + i_{D 2} (0)

(66)

According to equations (57) to (65), the diode currents i_D₁ and i_Do are exponential due to the R-L circuit formation between the equivalent series resistances and the leakage inductances. The diode current waveforms i_D₁ and i_Do are shown in Figure 13.

Figure 13.

During off-period corresponding diode currents.

Analysis of voltage stress of the power devices

The voltage stress is an important issue related to the cost and efficiency of converter. Due to low voltage rating and low r_DS(on) of power switch can be utilized in the circuit. Therefore, the switching and conduction losses can be reduced. In addition, the lower cost and higher efficiency of the converter can be received.

The voltage stress across power switch V_DS can be equaling the summation of DC-source V_i and magnetizing inductor voltage V_Lm in turned off period. Therefore, the voltage stress across power switch S₁ is

V_{DS} = \frac{1}{1 - D} \cdot V_{i}

(67)

M_{S} = \frac{V_{DS}}{V_{O}} = \frac{1}{(2 + n_{2} + n_{3}) - n_{3} D}

(68)

While the switch S₁ is turned on, the diodes D₁ and D_o are reverse-biased. Therefore, the voltage stresses of diodes D₁ and D_o is as follows

V_{D 1} = \frac{1}{1 - D} \cdot V_{i}

(69)

V_{Do} = \frac{1 + n_{2}}{1 - D} \cdot V_{i}

(70)

While the switching S₁ is turned off, the diode D₂ is reverse-biased. Therefore, the voltage stresses across D₂ is as follows

V_{D 2} = \frac{1 + n_{2} + 2 n_{3} - 2 n_{3} D}{1 - D} \cdot V_{i}

(71)

Experiment of the proposed converter

The converter is tested to operate at the 48 V dc-input voltage and the switching frequency f_s is 50 kHz. The output voltage and output power are specified as V_o = 400 V and P_o = 1 kW respectively, and by using the current mode PWM IC UC3845 to achieved performance of the circuit. From the above design procedure, the power switch is selected as IXFH120N20P which has low ON state resistance r_DS(on) of 22 mΩ and is rated at 200 V. The winding N₁:N₂:N₃ is obtained as 1:1:2. The diode D₁ selected as B30H150G is Schottky diode and is rated at 150 V, 30 A. The voltage stress of voltage diodes D₂ and D_O are larger than D₁. Schottky diodes are not suitable for utilized. Therefore, diodes D₂ and D_O are selected as fast diode DSEI8-06A which are rated at 600 V, 8 A. Table 1 lists the main components and parameter requirements for the prototype.

Table 1.

Components and parameters in the proposed converter.

Components	Specifications
MOSFET S₁	IXFH120N20P
Diode D₁	B30H150G
Diode D₂/D_o	DSEI8-06A
Magnetic core	MPP core
Coupled-inductor turns ratio	N ₁:N₂:N₃ = 1:1:2.2
Magnetizing inductor L_m	185 uH
Leakage inductor L_k₁	3.15 uH
Capacitor C₁	200 V/470 uF
Capacitor C₂	450 V/180 uF
Capacitor C_o	450 V/180 uF
PWM IC	UC3845

This section introduces the voltage waveform and current waveform at each point of the converter under a full load of 1 kW. Figure 14 shows the converter’s magnetizing inductance current i_Lm and the power switches V_GS and V_DS.

Figure 14.

Experimental coupled-inductor current and power switch voltage waveforms under various output power: (a) 250 W, (b) 500 W, (c) 750 W, and (d) 1 kW.

And as shown in Figure 15, when the output voltage V_O = 400 V, the power switch V_DS can be clamped to avoid high voltage stress. The voltage across the diodes D₁, D₂, and D_O are shown in Figure 16.

Figure 15.

Experimental switch voltage when V_i = 48 V and P_O = 400 V.

Figure 16.

Experimental voltage across diodes D₁, D₂, and D_O of the proposed converter with V_O = 400 V and P_O = 1 kW.

The cut-off voltage of V_D₁ and V_DO is less than the output voltage. The clamping circuit of the charging current i_D₁ is shown in Figure 17(a). The inrush current is caused by the leakage inductance of the coupled inductor while the power switch turned-off. Furthermore, the leakage inductance energy is recycled to the capacitor C₁ for further improve the efficiency of the converter. Figure 17(b) shows that the current i_D₂ of the secondary-side winding N₂ is connected in series with voltages V_i, V_C₁, and V_N₃ to charge capacitor C₂. Figure 17(c) depicts the output current i_Do of the energies of V_i, L_m, C₂, and N₂ charge output capacitor C_o and load R_o. As shown in Figure 18, the efficiency of the converter under different output powers P_O, where the maximum efficiency is about 96.5% at 200 W, and the efficiency is about 92.3% at a full load of 1 kW.

Figure 17.

Experimental current flow through diodes of the proposed converter with V_O = 400 V and P_O = 1 kW: (a) D₁, (b) D₂, and (c) D_O.

Figure 18.

The conversion efficiency with V_i = 48 V and V_o = 400 V under various output power (P_out).

Conclusion

This paper proposes a non-isolated high-boost DC/DC converter. The converter architecture combines switched capacitor technology, boost capacitor technology, and capacitor diode voltage doubler technology, not only can recover the leakage inductance energy on the coupled inductor, improve the conversion efficiency, but also has a higher voltage gain. In addition, the active clamp circuit limits the peak voltage on the V_DS of the power switch, reducing the voltage stress of the power switch. Based on the above conditions, this paper proposes that the converter architecture achieves high voltage gain, high efficiency, and effective suppression of voltage stress, and can be effectively applied to the conversion system of green energy grids and electric vehicle charging station.

Footnotes

Declaration of conflicting interests

The author(s) declared no potential conflicts of interest with respect to the research, authorship, and/or publication of this article.

Funding

The author(s) disclosed receipt of the following financial support for the research, authorship, and/or publication of this article: This research was sponsored by Ministry of Science and Technology of Taiwan under the Grant MOST108-2221-E-150-046 and NFU 108B1-061.

ORCID iD

Van-Tsai Liu

Author biographies

Van-Tsai Liu received his M.S. degree from Department of Information and Electronic Engineering, National Central University, Taoyuan, Taiwan in 1987. He is currently a professor in the Department of Electrical Engineering, National Formosa University, Yunlin, Taiwan. His research interests include intelligent control, electric vehicle applications, battery management system.

Kuo-Ching Tseng received his M.S. degree from Da-Yeh University and Ph.D. degree from National Cheng Kung University. He is currently a professor in the Department of Electronic Engineering, National Kaohsiung University of Science and Technology. His research interests include switching power converter designs and fuel cell power conversion systems.

Yue-Han Wu received his M.S. degree from Department of Electrical Engineering, National Formosa University, Yunlin, Taiwan in 2012. His research interests include step-up converter, high voltage gain power converter.

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Non-isolated high step-up DC/DC power converter with coupled-inductor

Abstract

Keywords

Introduction

Analysis of proposed high step-up DC/DC converter

Operation principle of the proposed converter in continuous conduction mode (CCM)

Steady-state analysis of the proposed converter in continuous conduction mode (CCM)

Effects of the ESRs on the semiconductor devices

Analysis of voltage stress of the power devices

Experiment of the proposed converter

Conclusion

Footnotes

Declaration of conflicting interests

Funding

ORCID iD

Author biographies

References