The optimal geometry parameters and impact of parasitic capacitance and resistance of sub-14nm SOI multi-fin FinFETs

Abstract

Nowadays FinFETs integrated into complex applications can fulfill the demand of new technology and make chips that can compute faster. Simultaneously various novel FinFETs structures come up constantly. In this brief, the impact of significant geometry parameters variations to device performance has been studied, such as fin height (H_fin), fin width (W_fin), fin spacing (S_fin), aspect ratio (W_fin/H_fin), and so on. In the result, we are able to determine the optimum device parameters for Multi-fin FinFETs. Meanwhile we analyze the parasitic gate capacitance and resistance of the multi-fin FinFETs using a conformal mapping method. To minimize the number of model fitting parameters, nondimensionalization technique is used. An effective lumped resistance model derived from distributed RC network is in use. Also, an analytical parasitic gate capacitance model is proposed, combined with parasitic capacitive couplings between source/drain fins and gates. Those analytical model can be applied for accurate circuit simulations of multi-fin FinFETs devices. The results presented in this paper can be of great help to device designers in designing 3-D devices as per their requirement.

Keywords

Optimized parameters device performance multi-fin FinFETs parasitic capacitance parasitic resistance conformal mapping

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