Exploring power reduction options for a single-chip multiprocessor through system-level modeling

Abstract

Moore's law predicts that fabrication processes will soon yield over a billion transistors on a single die. Over the past twenty years, the gap between the amount of available real estate on a chip and designer productivity has widened and continues to grow, so that designers are less able to make effective use of the increasing number of transistors on a chip. The primary problem in system-on-a-chip (SoC) design is no longer the limit on the number of resources. Rather, the development of new methodologies and system-level design tools is the challenge that lies ahead, as these have become essential to keeping costs low in the planning and construction of these systems. Designers have realized that the consideration of the overwhelming details at register-transfer level (RTL) early in development restricts design space exploration, inhibits trade-off evaluation, and results in increased time-to-market. In order to effectively utilize the available resources, the entry point of design flows in recent methodologies is at higher levels of abstraction, with consideration to significantly fewer details of the final hardware implementation.

In recent years, we have also seen the introduction of single-chip multiprocessors. As new tools and methodologies emerge for abstract system design, proposed solutions to the arising problems in the performance of single-chip multiprocessors can be implemented and evaluated more efficiently. For example, the amount of on-chip memory for such parallel systems continues to steadily rise, but so does the amount of power used by the memory system. In this work, we apply novel design methodology and tools to a single-chip multicore architecture, considering alternatives for power reduction of the storage components through system-level modeling.