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Abstract

A voltage mode capacitance multiplier for ultra-low frequency physiological signal processing is designed with a circuit model. With the proposed multiplier, a filter can achieve a cutoff frequency of 12 mHz with a 1 pF basic capacitance and a 10 kΩ resistor. The corresponding multiplication factor will be 1.35 × 10⁹. By changing the controlling terminal, the multiplication factor can be widely tuned from 1950 to 1.35 × 10⁹ and the corresponding filter cutoff frequency will be from 12 mHz to 8.15 kHz. According to the circuit model, to further increase the multiplication factor to decrease the chip area, more multiplication stages can be added to the feedback loop.

Keywords

Capacitance multiplier physiological signal circuit model widely tunable chip area

Introduction

Integrated circuits are potential building blocks in miniature medical instrumentations such as portable, wearable, and implantable devices.^1–8 Physiological signal processing after obtaining from sensors is an important part of the whole system. Most physiological signals are in the range of near direct current (DC) to 10 kHz. As a result, ultra-low frequency filters will be needed, which usually means large capacitance, large resistance, and small transconductance amplifier. Large resistance or capacitance will occupy a large chip area, which means a large system volume and high cost. It is not feasible for on-chip implementation. Besides, the values of passive components are sensitive to process conditions. As a result, circuits can be designed to be equivalent to the large passive component. Many groups have started to research in these fields. To get large grounded capacitance, current mode,^9–13 voltage mode,^14–16 active elements based,^17–27 and non-balance capacitance multipliers²⁸ have been designed. However, there are also some problems to be solved. Firstly, the tunable range should be increased to make the circuit suitable for more physiological signal processing. Secondly, the design method should be more transplantable. It should not be just for only one application. Thirdly, in the traditional current mode multiplier, there is a trade-off between increasing multiplication and decreasing power consumption, which should be improved.

In this paper, a voltage mode multiplier is designed based on a simple circuit model. By using a metal–oxide–semiconductor field-effect transistor level circuit to realize the component in the model, we obtained a very flexible and transplantable design method. A widely tunable range of multiplication can be achieved. More gain stages can be added in the feedback loop to further increase the multiplications to decrease the chip area.

Circuit design

A simple model of voltage mode capacitance multiplier can be shown in Figure 1. We can get the equivalent capacitance from this model

C_{e q} = C_{0} (1 + K)

(1)

Figure 1.

A simple model of voltage mode capacitance multiplier.

K + 1 is the multiplication factor and K is the total gain of the multiplication stages. The multiplication stages will be amplifiers. To get the equivalent capacitance in equation (1), the output signal must have the opposite direction with the input signal. The gain-controlling part will tune the multiplication factor by an external voltage. The structures and number of the amplification stages can be chosen according to specific applications based on this model.

In this paper, the specific circuit structure of the voltage mode capacitance multiplier will be decided in order to get widely tunable multiplication, which can be seen in Figure 2. There are three stages in the feedback loop, the first stage is a buffer, the second stage is a T-type inverting proportional amplifier to ensure a high gain as well as the opposite direction of input and output, and the third stage is a positive proportional amplifier. MA, MB, and MC are used as resistances. The equivalent capacitance can be expressed

C_{e q} = C_{0} (1 + \frac{R_{A} + R_{B}}{R_{1}} + \frac{R_{A} / / R_{B}}{R_{2}} \frac{R_{A} + R_{B}}{R_{1}} \frac{R_{C}}{R_{3}})

(2)

Figure 2.

The structure of the proposed capacitance multiplier.

By setting, (R_A+ R_B)/R₁, (R_A//R_B)/R₂, and R_C/R₃ as large values, a high multiplication factor can be achieved. R_C is the equivalent resistance of MC, R_B is the equivalent resistance of MB, and R_A is the resistance of MA. By changing the gate voltage of MA, MB, and MC, the resistance can be changed, and the equivalent capacitance and the multiplication factor will be widely tuned.

To ensure the equivalent capacitance in equation (2), the operational amplifier (OPA) in Figure 2 should have a high gain. For the traditional two-stage amplifier, the bandwidth will be too narrow for physiological signals with a range of nearly DC to 10 kHz when the gain is as high as 90 dB. Because for a specific structure, there will be a trade-off between bandwidth and gain. As a result, a three-stage amplifier is adopted in this paper as shown in Figure 3.

Figure 3.

The structure of the operational amplifier (OPA).

Based on the circuit model in Figure 1, more gain stages can be added in the feedback loop to further increase the multiplications to decrease the chip area. As a result, a transplantable and flexible design method of capacitance multiplier based on a circuit model is found.

Simulation results

The proposed capacitance multiplier is designed in 0.18 μm complementary metal–oxide–semiconductor (CMOS) technology with a supply voltage of 1.8 V. The dimensions of the components in the proposed circuit are shown in Table 1.

Table 1.

The dimensions of the devices in the proposed capacitance multiplier.

Device	Dimension	Device	Dimension	Device	Dimension
M0	2 μm/3 μm	M7	39.6 μm/0.3 μm	MR	15.9 μ/1 μ
M1	2.8 μm/1 μm	M8	13.9 μm/1 μm	R1	1 KΩ
M2	2.8 μm/1 μm	M9	39.6 μm/0.3 μm	R2	1 KΩ
M3	35 μm/0.4 μm	M10	0.66 μm/2.2 μm	R3	1 KΩ
M4	35 μm/0.4 μm	M11	0.66 μm/2.2 μm	MA	3 μm/3 μm
M5	15 μm/0.3 μm	M12	0.66 μm/2.2 μm	MB	3 μm/3 μm
M6	99.9 μm/0.19 μm	C_C	0.25 pF	MC	3 μm/3 μm

The layout of the circuit is shown in Figure 4. The area of the layout is about 116 μm × 71 μm. The parasitic parameter has been extracted from the layout. Both pre- and post-layout simulations are done with the circuit.

Figure 4.

The layout of the proposed capacitance multiplier.

The gain and bandwidth of the OPA are about 94 dB and 43 MHz as shown in Figure 5. The pre- and post-simulation have nearly the same result. According to the simulation result, we can see that the gain of the amplifier is large enough to be used as an ideal OPA, and the bandwidth of the amplifier is wide enough to process physiological signals.

Figure 5.

The frequency characteristics of the operational amplifier (OPA).

To verify the performance of the proposed circuit, the multiplier is connected with a resistor to form a simple first-order low-pass RC filter. As shown in Figure 6, the cutoff frequency of the filter changes from 12 mHz to 8.15 kHz when tuning V_C. The pre- and post-simulation curves are nearly coincident.

Figure 6.

The alternative current (AC) analysis of the filter output when tuning V_C.

The multiplication factor of the multiplier varies from 1950 to 1.35 × 10⁹ when tuning V_C as shown in Figure 7. The highest multiplication factor is obtained when V_C = 1.3 V.

Figure 7.

The multiplication factor under different control voltage V_C.

The transient simulation result of the filter output with a sine wave of different amplitude at 1 mHz as an input signal is shown in Figure 8.

Figure 8.

Transient analysis of the low-pass filter.

Corner analysis of the frequency characteristics of the RC filter when V_C= 1.3 V is shown in Figure 9. The cutoff frequencies under tt, ff, ss, snfp, and fnsp are 12 mHz, 1260 mHz, 179 mHz, 140 mHz, and 228 mHz. The simulation results are shown in Figures 7–9 all come from post-layout simulation.

Figure 9.

The corner analysis of the frequency characteristics of the low-pass filter.

The proposed circuit will be used in a low-frequency field, so the post-layout simulation results are expected to be very close to the actual situation. The terminal V_C can be tuned to find a suitable multiplication factor in actual testing after tape-out in the future.

A summary of performance comparison with other works is shown in Table 2. The maximum multiplication factor and the tuning range of this work are excellent. However, the power consumption of this work is average. Because the bandwidth of the OPA should be large enough to cover most kinds of physiological signals. There is a trade-off between bandwidth and power consumption under a certain OPA structure. A more optimized OPA structure should be developed to decrease the power consumption in the future.

Table 2.

Summary of performance comparison.

Ref.	Power	Supply	Process	Multiplication factor
²⁹	3 mW	—	0.13 μm CMOS	21⁴
³⁰	1.32 mW	1.3 V	0.5 μm CMOS	28
³¹	—	±0.75 V	0.18 μm CMOS	20–1200
³²	0.34 mW	±0.9 V	0.18 μm CMOS	98–455
³³	0.974 mW	±1.5 V	0.18 μm CMOS	5–50
This work	0.9 mW	1.8 V	0.18 μm CMOS	1950–1.35 × 10⁹

CMOS: complementary metal–oxide–semiconductor.

Conclusion

A capacitance multiplier design method based on a model is proposed in this paper. By using a three-stage structure in the feedback loop, the multiplication factor can be as high as 1.35 × 10⁹. When tuning the external voltage V_C, the multiplication factor of the multiplier varies widely from 1950 to 1.35 × 10⁹. To further increase the multiplication factor to decrease the chip area, more multiplication stages can be added to the feedback loop. As a result, a transplantable and flexible design method of capacitance multiplier based on a circuit model can be found in this paper. The proposed circuit can be used in the low-frequency field. Besides, the proposed structure can also be used in the circuit which needs a large on-chip passive component. The chip area and the system volume can be largely reduced by using the proposed method.

Footnotes

Author contribution

Li Yan carried out the concepts, performed the design and simulation work, and finished the manuscript writing.

Declaration of conflicting interests

The author declared no potential conflicts of interest with respect to the research, authorship, and/or publication of this article.

Funding

The author(s) disclosed receipt of the following financial support for the research, authorship, and/or publication of this article: This work was supported by Education Reform Project of Beijing Information Science and Technology University (Grant No. 2020JGYB41), National Natural Science Foundation of China (Grant No. 62101054), Foundation of the state key laboratory of Transducer Technology (Grant No. SKT2201), R&D Program of Beijing Municipal Education Commission (Grant No. KM202211232005).

ORCID iD

Yan Li

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A voltage mode grounded capacitance multiplier with widely tunable gain for ultra-low cutoff frequency filter

Abstract

Keywords

Introduction

Circuit design

Simulation results

Conclusion

Footnotes

Author contribution

Declaration of conflicting interests

Funding

ORCID iD

References