PLL-based nanoresonator driving IC with automatic parasitic capacitance cancellation and automatic gain control

Abstract

This paper presents a phase-locked loop (PLL) based resonator driving integrated circuit (IC) with automatic parasitic capacitance cancellation and automatic gain control. The PLL consisting of a phase frequency detector (PFD), a loop filter, and a voltage-controlled oscillator (VCO) makes the driving frequency to be locked at the resonant frequency. The resonator is modeled by Butterworth–Van Dyke equivalent circuit model with motional resistance of 72.8 kΩ, capacitance of 6.19 fF, inductance of 79.4 mH, and parasitic parallel capacitance of 2.59 pF. To mitigate the magnitude and phase distortion in the resonator frequency response, it is necessary to compensate for the parasitic capacitance. The proposed automatic parasitic capacitance cancellation loop is operated in the open-loop mode. In the automatic parasitic capacitance cancellation phase, the outputs of the transimpedance amplifier (TIA) at the lower and higher frequency than the resonant frequency (VH and VL), are compared, and the programmable compensation capacitor array matches the VH and VL using binary-searched algorithm to cancel the parallel parasitic capacitance. The automatic gain control (AGC) loop keeps the oscillation at the suitable amplitude, and the AGC output can be used as a measurement of the motional resistance. The AGC loop is also digitally controlled. The proposed resonator driving IC is designed in a 0.18-μm bipolar complementary metal oxide semiconductor double-diffused metal oxide semiconductor (BCDMOS) process with an active area of 3.2 mm². The simulated phase noise is −61.1 dBc/Hz at 1 kHz and the quality factor (Q-factor) is 59,590.

Keywords

Phase-locked loop automatic parasitic capacitance cancellation automatic gain control Butterworth-Van Dyke equivalent circuit model motional series resonant frequency

Introduction

As the development of internet of things (IoT) technologies, various sensor markets are continuously growing. Recently, nanotechnology-based nanoresonator sensor is of interests to expected to have various sensor applications with the growth of the nano/microelectromechanical system (NEMS/MEMS) sensor market. By the motional resistance or motional inductance detection method of a nanoresonator, it can be used for measuring physical properties of liquid, such as density or viscosity,^1–6 and it can be applied as bio sensors or chemical sensors that measure the blood glucose, and so on.

There are two main categories for the resonator driving system: open-loop system and closed-loop system. In open-loop system, resonant frequency and quality factor (Q-factor) can be obtained with the full frequency curve of a nanoresonator,⁷ but the additional input driving source with frequency sweeps near resonant frequency is required. In the case of high Q-factor of resonator, the sweep size of the input frequency should be fine. With unknown resonant frequency, it can be difficult to find the resonant frequency depending on the frequency sweep range and size. Also, there are limitations in obtaining the continuous changes in Q-factor or resonant frequency. In closed-loop system, self-sustained oscillator^8–11 circuit and phase-locked loop (PLL) architecture^4,12 are mainly used. Compared to the oscillator circuit, PLL architecture has better adaptability to resonators and better performance with large damped resonators.¹

This paper presents PLL-based nanoresonator driving integrated circuit (IC) with automatic parasitic capacitance cancellation and automatic gain control. The nanoresonator was modeled by Butterworth-Van Dyke equivalent circuit model^13–17 with motional series branch (resistance, inductance, and capacitance) and parallel parasitic capacitance. The purpose of the proposed nanoresonator driving IC is detection of the motional resistance, which is damping parameter of the mechanical lumped-parameter model. The nanoresonator model used in the proposed circuit has the motional series resonant frequency of 7.16 MHz, and the parallel capacitance of 2.59 pF. As the parasitic capacitance cause magnitude and phase distortions of frequency response and affect the resonant characteristic, the influence of the parasitic capacitance should be minimized. In this paper, a new method for the parasitic compensation is presented for the parasitic capacitance compensation. The automatic parasitic capacitance cancellation loop of the proposed nanoresonator driving IC automatically matches the programmable compensation capacitor array to the parasitic capacitance by using binary-searched algorithm, and compensate the parasitic capacitance properly.

PLL consists of phase frequency detector (PFD), loop filter, and voltage-controlled oscillator (VCO). PLL tracks the resonant frequency of the nanoresonator and keeps the oscillation frequency at the resonant frequency. The path through the AGC amplifier A₃, resistor R_REP and A₄, which is the replica path with the path through the AGC amplifier A₁, nanoresonator and TIA compensate the phase delay because of the AGC amplifier, nanoresonator, and TIA.

The automatic gain control loop (AGC)^11,18 keeps the oscillation amplitude properly, by automatically tracking the set reference voltage V_AGC. As the motional resistance can be obtained digitally by the AGC loop operation, the proposed circuit does not require an additional analog-to-digital converter (ADC).

The remainder of this paper is organized as follows. Section “Circuit implementation” describes the overall structure and compositions of the proposed scheme. Section “Circuit operation” describes the detailed operation principle of each mode (automatic parasitic capacitance cancellation loop, PLL, and AGC loop) of the proposed scheme. Section “Experimental results” shows the operation verification of the implemented circuit. The end of the paper concludes the proposed PLL-based nanoresonator driving IC.

Circuit implementation

Figure 1 shows the top architecture of the proposed PLL-based nanoresonator driving IC with automatic parasitic capacitance cancellation and AGC. The automatic parasitic cancellation loop mode and the AGC loop mode can be selected by switching operation. Before the operation of PLL and the AGC loop, the automatic parasitic capacitance cancellation loop is activated first to compensate the parasitic parallel capacitance of a nanoresonator.

Figure 1.

Top architecture of the proposed PLL-based nanoresonator driving IC with automatic parasitic capacitance cancellation and automatic gain control.

The automatic parasitic capacitance cancellation loop consists of 10-bit programmable compensation capacitors array C_comp, buffer A_P1, unity gain inverting amplifier A_P2, TIA, peak detector, sampling capacitors C_H and C_L, comparator COMP_APC, and successive approximation register (SAR) logic. In the parasitic capacitance cancellation loop phase, a higher frequency and a lower frequency compared with the resonant frequency is implied to the input terminal F_inH and F_inL, respectively. By the sequential operation of two switches F_{H_sel} and F_{L_sel}, the circuit is driven in higher frequency and lower frequency sequentially. In the parasitic capacitance cancellation phase, R_AGC and the gain of the AGC amplifiers (A₁, A₂, and A₃) has a static value.

PLL consists of PFD, VCO, and loop filter. The phase of TIA output and VCO output are compared by two comparators COMP_PLL1 and COMP_PLL2, and PFD output that proportional to the phase difference controls VCO. The PFD output voltage is applied to the VCO and keeps the VCO output frequency at the resonant frequency. The AGC loop consists of 9-bit programmable resistor array R_AGC, AGC amplifier, TIA, peak detector, comparator COMP_AGC, and SAR logic register. The DC voltage input terminal V_AGC at the comparator COMP_AGC is the reference voltage that is compared with the peak voltage of the TIA output. The reference voltage V_AGC can be arbitrarily set to a desired oscillation amplitude.

The nanoresonator model used in the proposed IC is shown in Figure 2. The nanoresonator was modeled by Butterworth-Van Dyke equivalent circuit model with the motional series resonant frequency of 7.16 MHz (the motional resistance of 72.8 kΩ, the motional inductance of 79.4 mH, the motional capacitance of 6.19 fF and the parasitic parallel capacitance C_p of 2.59 pF.

Figure 2.

Butterworth-Van Dyke equivalent circuit model of the nanoresonator.

Figure 3 shows the charge pump PFD (CPPFD)¹⁹ implemented in the proposed IC. The CPPFD is implemented with two D flip-flops, source current I_SRC, and sink current I_SNK. I_SRC and I_SNK which has the current value of 12 µA in the proposed circuit force the current into or out the loop filter. The loop filter is implemented with second-order passive loop filter with R_LF of 600 Ω, C_LF of 80 pF, and C_F of 8 pF. The CPPFD compares the phase of VCO output and of TIA output, and locks the oscillation frequency at the resonant frequency of the nanoresonator. To avoid a dead zone region of the CPPFD, reset input is delayed using two inverter cells.

Figure 3.

Schematic of the charge pump phase frequency detector (CPPFD).

Figure 4 shows the schematic of operational amplifier (op-amp) used in TIA, AGC amplifier, and peak detector. The op-amp is implemented with rail-to-rail folded cascode architecture and Monticelli’s class-AB output stage.²⁰ For the wide input range, M1–M4 forms rail-to-rail input stage. M9–M12, M17, and M18 constitute Monticelli’s class-AB output stage to achieve power efficiency. C_m1 and C_m2 is used to nested-Miller compensation capacitor to secure frequency response stability.

Figure 4.

Schematic of the rail-to-rail folded cascode amplifier with Monticelli’s class-AB output stage.

Circuit operation

Automatic parasitic capacitance cancellation loop

In the Butterworth-Van Dyke equivalent circuit model, the MSRF ω_rs of the nanoresonator that parasitic capacitance C_p is ignored is expressed as:

ω_{rs} = \frac{1}{\sqrt{L_{m} C_{m}}}

(1)

In the case of C_p >> C_m, the parallel resonant frequency ω_rp that C_p is considered can be expressed as:¹⁶

ω_{rp} = ω_{rs} \cdot \sqrt{1 + \frac{C_{m}}{C_{p}}}

(2)

The equations (1) and (2) indicate that parasitic capacitance affect the frequency response of the resonator, and it should be compensated properly.

As shown in Figure 5, if the parasitic capacitance C_p is not compensated, the resonator no more has a band-pass filter characteristic having an accurate resonant frequency, and the gain continuously increases or decreases with the variation of frequency. By taking advantage of this these characteristics, the automatic parasitic capacitance cancellation loop operates by the method of comparing the output voltage by sequentially applying a low-frequency signal input and a high-frequency signal input compared to the resonant frequency.

Figure 5.

Frequency response of a nanoresonator with and without parasitic capacitance.

Figure 6 shows the connection status of the automatic parasitic capacitance cancellation loop mode. A high-frequency input and a low-frequency input is applied to the input terminals F_inH and F_inL, respectively and as shown in the timing diagram of Figure 7, the nanoresonator is driven in high-frequency input and low-frequency input sequentially by operation of two switches F_{H_sel} and F_{L_sel}. The nanoresonator and the compensation capacitor array C_comp is driven with anti-phase by the buffer A_P1 and the unity gain inverting amplifier A_P2. The output current of nanoresonator driven in each input signal is converted to voltage and amplified by TIA, and each peak voltage of TIA output is stored in capacitors C_H, and C_L. The comparator COMP_APC compares voltage values stored in C_H and C_L, and the 10-bit programmable compensation capacitor array C_comp is controlled by the method of binary-searched algorithm using 10-bit SAR logic register. This operation is repeated until the compensation capacitance C_comp matches the parasitic capacitance C_p. C_comp is driven in anti-phase to the nanoresonator driving input using unity gain inverting amplifier, and when C_comp is equal to C_p, C_p is compensated.

Figure 6.

Circuit connection status of automatic parasitic capacitance cancellation loop operation.

Figure 7.

Timing diagram of automatic parasitic capacitance cancellation loop.

Figure 8 shows the conceptual frequency response of the nanoresonator during the automatic parasitic capacitance cancellation loop operation, and it briefly shows the process of matching the compensation capacitor C_comp to the parasitic capacitance C_p. Before compensation, the initial frequency characteristic of the nanoresonator is shown as in Figure 5. As the automatic parasitic capacitance cancellation loop operates, the output at the frequency of F_inH and F_inL is compared and C_comp is adjusted using SAR control. In this process, over compensation and under compensation of C_p is repeated, tracking the point where the gain at the frequency of F_inH and F_inL are same, that is, the point where C_comp is matched to C_p.

Figure 8.

Conceptual frequency response of the nanoresonator during the automatic parasitic capacitance cancellation loop operation.

PLL and Automatic gain control loop

After the parasitic capacitance is compensated by the operation of the automatic capacitance cancellation loop, PLL, and AGC loop mode are activated. Figure 9 shows the connection status of PLL and AGC loop mode. The current output of the nanoresonator driven by VCO output is converted to voltage and amplified by TIA and the peak voltage of TIA output is compared to set reference voltage V_AGC. The comparator COMP_AGC compares the peak voltage of TIA output and V_AGC, and 9-bit programmable resistor array R_AGC is controlled by the method of binary-searched algorithm using 9-bit SAR logic register. As R_AGC is controlled, the gain of the circuit is controlled and the peak voltage of the TIA output automatically tracks the reference voltage V_AGC.

Figure 9.

Circuit connection status of automatic gain control loop operation.

The motional capacitance C_m and the motional inductance L_m of the nanoresonator driven in resonant frequency are canceled each other out and if the parasitic capacitance C_p is compensated properly, the TIA output can be expressed as:

V_{O, TIA} = \frac{R_{AGC}}{R_{2}} \cdot \frac{R_{TIA}}{R_{m}} \cdot V_{IN}

(3)

The motional resistance R_m can be expressed as:

R_{m} = \frac{R_{AGC} \cdot R_{TIA}}{R_{2}} \cdot \frac{V_{IN}}{V_{O, TIA}}

(4)

As shown in the equations, R_m can be obtained by R_AGC, which can be obtained digitally from the SAR logic register.

Assuming the nanoresonator as a narrow-band mechanical bandpass filter, the fundamental frequency of V_in is the natural frequency of the nanoresonator. The C_F is about ten times smaller than C_LF, the open-loop gain of the PLL can be approximated as:

G (s) ≃ \frac{1}{2 π} \cdot I_{CP} \cdot K_{VCO} \cdot \frac{sRC + 1}{s^{2} C_{1}}

(5)

Where I_CP is the charge pump current and K_VCO is the voltage-to-frequency conversion coefficient of the VCO. Thus, the simplified closed-loop transfer function can be express as:

H (s) = \frac{\frac{I_{CP}}{2 π C_{LF}} \cdot K_{VCO} \cdot (R C_{LF} + 1)}{s^{2} + \frac{I_{CP}}{2 π} \cdot K_{VCO} \cdot Rs + \frac{I_{CP}}{2 π C_{LF}} \cdot K_{VCO}}

(6)

Experimental results

Figure 10 shows the layout of the proposed PLL-based nanoresonator driving IC with automatic parasitic cancellation and automatic gain control. The proposed IC is designed with a 0.18-μm bipolar complementary metal oxide semiconductor double-diffused metal oxide semiconductor (BCDMOS) process with an active area of 3.2 mm².

Figure 10.

Layout of the proposed PLL-based nanoresonator driving IC.

The op-amp shown in Figure 4 is implemented with unit gain bandwidth (UGBW) of hundreds of mega-hertz to drive the nanoresonator model with the resonant frequency of 7.16 MHz. Figure 11 shows the loop gain simulation results of the op-amp. The op-amp has DC gain of 82.2 dB, and UGBW of 260 MHz, which is sufficient to drive the nanoresonator with 7.16 MHz of resonant frequency. The op-amp has the phase margin of 50° and secures the frequency stability.

Figure 11.

Loop gain simulation results of the rail-to-rail folded cascode amplifier with class-AB output stage.

Figure 12 shows the simulation result of the automatic parasitic capacitance cancellation loop. The 10-bit programmable compensation capacitor array C_comp implemented with the unit capacitance of 33.4 fF matches the 2.59 pF of the parasitic capacitance C_p of the nanoresonator at digital register input of 76 or 77 in decimal. The SAR logic digital output controls the compensation capacitor array C_comp, comparing the output at the frequency of F_inH and F_inL, as shown in Figure 8. The simulated SAR logic register digital output is 76 and the parasitic capacitance is compensated properly.

Figure 12.

Digital output simulation result of the automatic parasitic capacitance cancellation loop.

Figure 13(a) shows the time domain simulation result of AGC loop when the motional resistance R_m is 10 kΩ, and the reference voltage V_AGC is 1.2 V. The oscillation frequency is locked at 7.16 MHz, which is close to the resonant frequency of the nanoresonator. The peak detector output of the black line automatically tracks the reference voltage V_AGC. Figure 13(b) shows the digital output of the AGC loop under the same condition and the simulated digital output is 13 in decimal.

Figure 13.

Simulation result of automatic gain control loop: (a) TIA and peak detector output and (b) digital output.

Figure 14 shows the motional resistance R_m detection simulation. Digital output of the AGC loop is simulated under the variation of the motional resistance R_m from 10 to 100 kΩ with intervals of 10 kΩ. The digital outputs for each resistance was non-linearity fitted with polynomial and digital outputs that vary linearly with the variation of R_m are obtained. The simulated non-linearity between R_m and digital output is 0.9% FSO.

Figure 14.

Motional resistance R_m detection simulation result.

Figure 15 shows fast Fourier transform (FFT) simulation result of the proposed PLL-based nanaoresonator driving IC when the motional resistance R_m is 10 kΩ, and reference voltage V_AGC is 1.2 V. The proposed nanoresonator driving IC has 59,590 of Q-factor and −61.1 dBc/Hz of phase noise floor at 1 kHz offset.

Figure 15.

FFT simulation result of the proposed PLL-based nanoresonator driving IC.

The performance of the proposed PLL-based nanoresonator driving IC with automatic parasitic capacitance cancellation and automatic gain control is summarized and compared with other method of driving resonator is shown in Table 1. As the parallel parasitic capacitance of the nanoresonator affects the frequency characteristics of the nanoresonator, the parasitic compensation included, and new method of automatically compensating for the parasitic capacitance is proposed.

Table 1.

Performance summary of the proposed PLL-based nanoresonator driving IC and comparison with other studies.

Method	Technology (µm)	Frequency (MHz)	Q-factor	Phase noise at 1 kHz (dBc/Hz)	Parasitic cancellation
This work	0.13	7.16	59,590	−61.1	Yes
Seth et al.⁹	0.18	20	160,000	−131	No
Nabki and El-Gamal¹⁸	0.18	8.29	1,040	−89	No
Wojciechowski et al.²²	0.35	101.71	3,100	−90.6	No
Johnston et al.²¹	0.18	864	1257	−68	No

Conclusion

As nanotechnology-based sensor is expected to have various sensor application, nanoresonator can be applied as a bio/chemical sensor by the method of detecting the motional inductance or the motional resistance. This paper presents PLL-based nanoresonator driving IC with automatic parasitic capacitance cancellation and automatic gain control. The purpose of the proposed IC is to detect the motional resistance of a nanoresonator. To compensate the phase or the magnitude distortion of the frequency response, the parallel parasitic capacitance of the nanoresonator should be compensated. The automatic parasitic capacitance cancellation loop automatically tracks and compensate the parasitic capacitance of a nanoresonator by using binary-searched algorithm. The automatic gain control loop automatically tracks the reference voltage and control the gain of the circuit, and maintains the oscillation amplitude properly. The motional resistance can be detected by digital output of the AGC loop. As the proposed circuit does not require an additional ADC to obtain the motional resistance digitally, area and power efficiency can be achieved. The proposed IC is designed with a 0.18-μm bipolar complementary metal oxide semiconductor double-diffused metal oxide semiconductor (BCDMOS) process with an active area of 3.2 mm². The simulated phase noise is −61.1 dBc/Hz at 1 kHz and the Q-factor is 59,590.

Footnotes

Acknowledgements

The EDA tool was supported by the IC Design Education Center (IDEC), Republic of Korea.

Declaration of conflicting interests

The author(s) declared no potential conflicts of interest with respect to the research, authorship, and/or publication of this article.

Funding

The author(s) disclosed receipt of the following financial support for the research, authorship, and/or publication of this article: This work was supported by the Electronics and Telecommunications Research Institute (ETRI) Grant funded by the Korean government (20ZB1155, Development of Core Technologies for Implantable Active Devices). This work was also supported by a grant to Bio-Mimetic Robot Research Center Funded by Defense Acquisition Program Administration, and by Agency for Defense Development (UD190018ID).

ORCID iD

Hyunwoo Heo

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