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Research article

First published 2006-5

Case study of gate-level logic simulation on an extremely fine-grained chip multiprocessor

Pei Gu, Uzi Vishkin

Journal of Embedded Computing

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Research article

First published 2014-1

Planning-Level Tool for Assessing and Optimizing Gate Layout for Marine Container Terminals

Chu Cong Minh, Nathan Huynh

Transportation Research Record: Journal of the Transportation Research Board

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Research article

First published 1975-10

Design of Optimal Two-Level Logic Networks Using Nor,and,Nand,or Gates

A. L. Frisiani

International Journal of Electrical Engineering & Education

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Research article

First published 2012-8

The effect of acute exogenous melatonin on P50 suppression in healthy male volunteers stratified for low and high gating levels

Ebru Ucar, Emilia K Lehtinen, Birte Y Glenthøj [...]

Journal of Psychopharmacology

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Research article

First published 1993-4

Two Factors Contributing to Elementary School Teachers' Predictions of Students' Scores on the Gates-MacGinitie Reading Test,Level D

John G. Freeman

Perceptual and Motor Skills

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Research article

First published 1991-11

Investigating simulation of hardware at various levels of abstraction and timing back-annotation of dataflow descriptions

Zainalabedin Navabi, Mehran Massoumi

SIMULATION

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Research article

First published 2009-04

A Multiway Design-driven Partitioning Algorithm for Distributed Verilog Simulation

Lijun Li, Carl Tropper

SIMULATION

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Other

First published 1997-02

Mathematics in Context: Opening The Gates to Mathematics for All t the Middle Level

Margaret R. Meyer

NASSP Bulletin

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Research article

First published 2022-2

Embedded linear model predictive control in field-programmable gate array using register-transfer level implementation and floating-point representation applied to a quadrotor system model

Alceu Bernardes Castanheira de Farias, André Murilo, Renato Vilela Lopes

Proceedings of the Institution of Mechanical Engineers,Part I: Journal of Systems and Control Engineering

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Research article

First published 2019-8

A framework for high-level simulation and optimization of fine-grained reconfigurable architectures

Muhammad Adeel Pasha, Umer Farooq, Bilal Siddiqui

SIMULATION

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