Floorplanning is the initial step in the process of designing layout of the chip. It is employed to plan the positions and shapes of modules during the process of VLSI Design cycle to optimize the cost metrics like layout area and wirelength. In this paper, a Hybrid Particle Swarm Optimization-Firefly (HPSOFF) algorithm is proposed which integrates Particle Swarm Optimization (PSO), Firefly (FF) and Modified Corner List (MCL) algorithms. Initially, PSO algorithm utilizes MCL algorithm for non-slicing floorplan representations and fitness value evaluation. The solutions obtained from PSO are provided as initial solutions to FF algorithm. Fitness function evaluation and floorplan representations for FF algorithm are again carried out using MCL algorithm. The proposed algorithm is illustrated using Microelectronics Centre of North Carolina (MCNC) and Gigascale Systems Research Centre (GSRC) benchmark circuits. The results obtained are compared with the solutions derived from other stochastic algorithms and the proposed algorithm provides better solutions for both the benchmark circuits.
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