Design of a Gigabit Host-Network Interface

Abstract

We have proposed a new architecture called Axon that meets the challenges of delivering high network bandwidth directly to applications. Its novel aspects include: an integrated design of host and network interface hardware, operating systems, and communication protocols; the proper division of hardware and software function; reorganisation of end-to-end protocols to take advantage of the increased functionality of the emerging high speed internetworks; and a pipelined interface between the network and host memory with no packet buffering.

The pipelined network interface performs critical per packet processing in hardware as packets flow through the pipeline, without imposing any store-and-forward buffering of packets. This requires the design of error and flow control mechanisms to be simple enough for implementation in the network interface hardware, while providing the functionality required by applications.

This paper describes the design of the host-network interface, and, in particular, the hardware design of the critical per packet processing with emphasis on error and flow control. An extensive simulation model of the network interface hardware has been used to determine the feasibility and performance of hardware implementation of these functions.