A novel VLSI architecture for a fuzzy inference processor using Gaussian-shaped membership function

Abstract

The widespread application of fuzzy logic in various fields has been hindered by the problem of low speed of operation of fuzzy processors. Both hardware and software approaches have been adopted to increase the speed of operation of the fuzzy processors in general and inference processing in particular. To improve the inference processing, the calculation of matching degree (MD) between the fuzzified input and the antecedent membership functions (MF) has to improve, as it needs very high latency and limits the overall inference performance. In this paper, a novel architecture of a MAX-MIN circuit, used for calculating the MD between two Gaussian-shaped MF's, used first time, has been proposed. The proposed architecture is area, power, speed efficient and flexible in comparison to existing architectures using trapezoid-MF, as the number of multiplexing and subtracting operations has been reduced. Further, based on the novel architecture of MAX-MIN calculator circuit, a novel fuzzifier, fuzzy decoder, fuzzy inferencing system and a complete fuzzy inference processor have been proposed and analyzed. The VHDL modeling and XILINX and Vertex based FPGA implementation of all proposed architectures have been performed.