Software and hardware co-design of AI high-rate chips for parallel training of edge intelligence

Abstract

With the digital transformation of information technology and industry, the applicability scenarios of edge intelligent terminals are expanding. AI chips have become one of the mainstream core devices of edge terminals. How to select suitable AI chips according to application scenarios through systematic analysis has become an urgent problem to be solved. This paper first provides a comparative analysis of the technical architecture and advantages and disadvantages of AI chips; then proposes a low implementation complexity, multi-code rate fusion LDPC parallel coding structure, and an encoder chip design scheme using this structure for high-speed digital transmission applications. Based on the TSMC 130 nm CMOS standard cell library, the encoder chip can achieve a throughput rate of 1.6 Gbps at 200 MHz clock and consume only 184.3 m W. Compared with the LDPC encoder chip with the same throughput rate designed in the conventional architecture, this solution can reduce the storage space requirement to 18.52% of the conventional architecture. The proposed encoding chip design solution not only maintains high performance but also significantly reduces the demand for storage space, making it a good choice for resource-constrained environments.