Hazard-free self-timed design: methodology and application

Abstract

This paper introduces an original methodology for hazard-free self-timed design, assuming the worst conditions for robustness. Hazards are classified under three types. Equation hazards are eliminated by an optimal covering. A new variable, labeled state-trajectory is proposed: its integrity guarantees immunity to function hazards. The choice of the delay model for implementation guarantees immunity to logic hazards. Signal-transition graph constraints support safe interaction with synchronous processes. The method was applied to the VLSI CMOS implementation of a router for a parallel machine. Specific cells are designed. Measured performances are presented.