Register-Transfer Level Transformations for Low-Power Data-Paths

Abstract

Decisions taken at the earliest steps of the design of an electronic circuit may have a significant impact on the characteristics of the final implementation. This paper illustrates how power consumption issues can be tackled at algorithmic and architectural level during the design of application-specific integrated circuits (ASICs) in an embedded system scenario. A set of RTL transformations aiming at reducing power consumption are proposed and the potential benefits evaluated. The common idea behind the transformations is to reduce the activity of the data-path functional units (e.g., adders, multipliers) by minimizing the switching activity of their input operands. Functional units contribute highly to the power consumption of the data-path. Preliminary evaluations obtained by simulation show that significant improvements can be achieved. Finally, the paper demonstrates how some of the presented transformations can be automated and incorporated in high-level synthesis tools.