Abstract
Terabit IP switch router is a key to the success of next generation Internet (NGI) with its backbone capacity supporting exponentially increasing traffic. The challenges in designing a terabit IP switch router include (1) a large capacity switch fabric providing high speed interconnection for a number of smaller capacity router modules, and (2) a fast arbitration scheme resolving output contention within stringent time constraint while achieving high throughput and low delay. In this paper, an input–output buffered switch architecture with a speedup of two is employed; our simulation results show that it can nearly achieve the theoretic bound in average delay/throughput performance of an output buffered switch. We propose a
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