Memory power optimization of hardware implementations of multimedia applications onto FPGA platforms

Abstract

An optimization methodology that combines high-level exploration with Register Transfer Level (RTL) design for the power-efficient estimation of motion estimation algorithms on a system comprised by an FPGA and an external memory is presented. Low power consumption is achieved by implementing an optimum on-chip memory hierarchy inside the FPGA, and moving the bulk of required memory transfers from the internal memory hierarchy instead of the external memory. A case study of three popular multimedia kernels is performed for a number of different FPGA devices. Comparisons among implementations with and without this optimization, prove that great power efficiency can be achieved while satisfying performance constraints.