A low-power digital processing circuit for capacitive accelerometer

Abstract

A low power consumption digital processing circuit with large dynamic range and low noise density for micromachined capacitive accelerometer is proposed. To reduce the power consumption, the sampling rate and the number of logic units used are analyzed. We lower the sampling rate to 2.5 MHz that is only 1/16 of previous scheme. At this frequency, the dynamic range is still as high as 120 dB that has been tested, while the dynamic power is as low as 5.4 mW that is only about 1/16 of previous scheme. To reduce the amount of logic units, we adopt square-wave demodulator instead of sinusoidal demodulator (realized by coordinate rotation digital computer algorithm). The entire digital processing circuit with square-wave demodulator uses 577 slice registers, about 1/10 of the circuit with sinusoidal demodulator. The dynamic power is even reduced to 0.54 mW. Most of all, almost no additional noise is added into this circuit, and the output noise density is as low as 0.01 mg/√Hz.