Sage Journals: Discover world-class research

Abstract

In this paper, a novel, nanoscale, metal–oxide–semiconductor field-effect transistor (MOSFET) with gate-to-source/drain non-overlapped and high-k spacer structure has been demonstrated to reduce gate leakage current for the first time. The gate leakage behaviour of the novel MOSFET structure has been investigated with the help of a compact analytical model and Sentaurus simulation. The fringing gate electric field through the dielectric spacer induces an inversion layer in the non-overlap region to act as an extended source/drain region. It is found that the optimal gate-to-source/drain non-overlapped and high-k spacer structure reduces the gate leakage current to a great extent compared with an overlapped structure. Further, the proposed structure has an improved off-current, sub-threshold slope, and drain-induced barrier-lowering characteristic. It is concluded that this structure solves the problem of high leakage current without introducing the extra series resistance.

Keywords

gate tunnelling current analytical model spacer dielectrics drain-induced barrier lowering sub-threshold slope

Get full access to this article

View all access options for this article.

References

Choi

C.-H.

Nam

K. Y.

Dutton

R. W.

Impact of gate direct tunneling current on circuit performance: a simulation study. IEEE Trans. Electron Devices, 2001, 48(12), 2823–2829.

International technology roadmap for semiconductors, available from http://public.itrs.net/Files/2001ITRS/Home.html.

Taur

CMOS design near the limits of scaling. IBM J. Res. Dev., 2002, 46(2/3), 213–222.

Sirisantana

Wei

Roy

High performance low–power CMOS circuits using multiple channel length and multiple oxide thickness. In Proceedings of IEEE International Conference on Computer Design, 17–20 September 2000, pp. 227–232.

Hamzaoglu

Stan

Circuit-level techniques to control gate leakage for sub 100 nm CMOS. In Proceedings of International Symposium of Low Power Electronics and Design, 12–14 August 2002, pp. 60–63.

Roy

Mukhopadhyay

Meimand

H. M.

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS crcuits. Proc. IEEE, 2003, 91(2), 305–327.

Lee

Blaauw

Sylvester

Analysis and minimization techniques for total leakage considering gate oxide leakage. In Proceedings of Design Automation Conference, 2–6 June 2003, pp. 175–180.

Lee

Blaauw

Sylvester

Gate oxide leakage current analysis and reduction for VLSI circuits. IEEE Trans. Very Large Scale Integrated Syst., 2004, 12(2), 155–166.

Sultania

A. K.

Sylvester

Sapatnekar

S. S.

Tradeoffs between gate oxide leakage and delay for dual T_ox circuits. In Proceedings of the Design Automation Conference, San Diego, California, 7–11 June 2004, pp. 761–766.

10.

Sirisantana

Roy

Low-power design using multiple channel lengths and oxide thicknesses. IEEE Des. Test Comput. Mag., 2004, 21(1), 56–63.

11.

Mohanty

S. P.

Kougianos

Modeling and reduction of gate leakage during behavioral synthesis of nano CMOS circuits. In Proceedings of the Nineteenth IEEE International Conference on VLSI design (VLSID), Hydrabad, India, 3–7 January 2006, pp. 1063–1067.

12.

Lee

H.-J.

Lee

J.-H.

Shin

H.-C.

DC and AC characteristics of sub-50-nm MOSFETs with source/drain-to-gate non-overlapped structure. IEEE Trans. Nanotechnol., 2002, 1(4), 219–225.

13.

Sundararajan

Parhi

Low power synthesis of dual threshold voltage (DVT) CMOS VLSI circuits. In Proceeding of ISLPED, San Diego, California, 16–17 August 1999, pp. 139–144.

14.

Sultania

Sylvester

Sapatnekar

Transistor and pin reordering for gate oxide leakage reduction in dual T_ox CMOS (DTOCMOS) circuits. In Proceedings of the Twenty-second ICCD, San Jose, California, USA, 11–13 October 2004, pp. 174–175.

15.

Beak

K.-J.

Kim

J.-K.

Kim

Y.-S.

K.-Y.

Device optimization of n-channel MOSFETs with lateral asymmetric channel doping profiles. Trans. Elect. Electron. Mater., 2010, 11(1), 15–19.

16.

Ghani

Mistry

Packan

Thompson

Stettler

Tyagi

Bohr

Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors. In Technical Digest of VLSI Symposium, Honolulu, Hawaii, 13–15 June 2000, pp. 174–175.

17.

Schuegraf

K. F.

Hole injection SiO₂ breakdown model for very low voltage lifetime extrapolation. IEEE Trans. Electron Devices, 1994, 41(5), 761–767.

18.

Lee

W.-C.

Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunnelling. IEEE Trans. Electron Devices, 2001, 48(7), 1366–1373.

19.

Pregaldiny

Lallement

Mathiot

Accounting for quantum mechanical effects from accumulation to inversion, in a fully analytical surface potential-based MOSFET model. Solid-State Electron., 2004, 48(5), 781–787.

20.

Taur

Ning

T. H.

Fundamentals of modern VLSI devices, 1998 (Cambridge University Press, New York).

21.

Chung

S.S.-S.

T.-C.

An analytical threshold-voltage model of trench-isolated MOS devices with non-uniformly doped substrates. IEEE Trans. Electron Devices, 1992, 39(3), 614–622.

22.

Gate leakage reduction through the use of a gate-to-source/drain non-overlapped metal–oxide–semiconductor field-effect transistor structure

Abstract

Keywords

Get full access to this article

References