Using Declarative Specifications and Case-based Planning for System Synthesis

Abstract

Synthesis of pragmatic systems from high-level specifications requires representation and application of both functional requirements and constraints. This work presents a language for representing requirements and constraints in VHDL design representations and a prototype care-based synthesis system. VSPEC is an annotation language for VHDL developed to support axiomatic representation of requirements for system synthesis. VSPEC descriptions serve as synthesis goals and verification criteria. A prototype case-based synthesis system is also presented that uses VSPEC requirements as goal statements and descriptions of potential solutions. This prototype system demonstrates how synthesis can be performed at the systems level and how constraints can be used to implement a simple concurrent engineering process.