A reconfigurable adder for an efficient MAC in DNNs applications on edge device

Abstract

AI devices, whether they are related to medical surgery, autonomous driving, or contactless delivery, use DNNs as an inbuilt architecture. Deployment of DNNs on resource-critical devices is still quite challenging due to huge resource requirements. Therefore, in this research paper, we propose a reconfigurable adder in the accumulation part of the MAC operation, which as a result makes DNN applications less compute intensive and lighter. A reconfigurable adder is tested in both convolution and dense parts of different DNN architectures for architecture performance and its edge deployment related matrices. In terms of architecture performance related parameters like accuracy, precision, recall, F1 score, our proposed customized architecture is quite in-line with conventional DNNs architectures (LeNet-5, AlexNet-Lite, GEMM) for three dataset MNIST, Fashion MNIST and AtoZ Handwritten. For edge deployment related matrices, our proposed architecture on CPU, reduces model size up to 61%, cpu utilization up to 50% at the expense of increasing inference time up to 36% due to minimal memory uses in architecture simulation. We also perform deployments of our proposed customized architecture (LeNet-5, AlexNet-Lite) on Jetson Nano as an edge device. Its result for parameters like cpu utilization, memory usage and model size is quite in line with software emulation of baseline architecture on CPU, inference time of our proposed architecture is 3 to 4 times as compared to the standard architecture. Jetson Nano, being a GPU supported device, works well for parallelism in comparison to sequential/parallel as our customized architecture. Higher inference time is due to trade off between terminology of architecture and supported edge devices.