Simulation-driven optimization of pentacene based organic thin-film transistors (OTFTs) for next-generation flexible electronics: A novel ditch layer architecture approach

Abstract

This study presents a rigorous simulation-based investigation of pentacene-based organic thin-film transistors (OTFTs) employing innovative ditch layer architectures with strategically engineered p+ doped regions embedded within the dielectric structure, demonstrating substantial performance superiority over conventional configurations. Systematic analysis of bottom-gate, bottom-contact (BGBC) architectures across horizontal, vertical, and omnidirectional doping geometries reveals exceptional scalability for channel lengths spanning 50 nm to 1  $\mu$ m. Precision-controlled thickness optimization at 60 and 50 nm effectively addresses critical fabrication challenges—dewetting mitigation, strain engineering, and stress management—while achieving subthreshold swing values of 36.33–42.14 mV/dec, constituting an 81% improvement over non-optimized structures (192.65 mV/dec). The proposed architecture augments charge transport efficiency by 23% and achieves exceptional $I_{ON}$ / $I_{OFF}$ ratios of $3.57\times 0^{12}$ , representing four-to-six orders of magnitude enhancement over conventional organic transistors. Comprehensive Silvaco ATLAS simulations demonstrate that optimized bottom-gate top-contact structures deliver 3.65 $\times$ superior drain current density while BGBC configurations reduce off-state leakage by 36%. Comparative benchmarking establishes $I_{ON}$ / $I_{OFF}$ enhancement factors of 57 $\times$ , 41 $\times$ , 37 $\times$ , and 25 $\times$ versus carbon nanotube FETs, FinFETs, gate-all-around FETs, and negative capacitance FETs, respectively. The optimized device maintains physically realistic pentacene mobility approaching $\sim$ 2 cm ${}^2$ /V $\cdot$ s while achieving 54% energy reduction and 69% static noise margin enhancement, advancing ambient-fabricable flexible organic electronics.