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Abstract

This article presents the performance analysis of reconfigurable multiple-switch fault-tolerant multiport DC–DC converters for renewable-based hybrid standalone applications. Detailing various switch faults, two topologies have been studied, each accompanied by a thorough exploration of operating scenarios. While the first topology is capable of addressing faults occurring in single or multiple switches, it falls short of achieving complete fault tolerance. In order to address this limitation, a fully fault-tolerant topology has been introduced, specifically designed to manage all potential combinations of multiple switch faults. To verify the efficacy of the topologies across various operating scenarios, laboratory prototypes were developed and employed. The empirical findings from real-time testing of the reconfigurable fault-tolerant topologies guarantee regulated voltage with uninterrupted supply in both charging and discharging operations of the energy storage device. The performance of the topologies related to stress, loss, reliability, and cost has also been investigated. This article also presents a comparative analysis of reconfigurable fault-tolerant converters with similar topologies.

Keywords

Reconfigurable multiple switch faults hybrid standalone applications fault-tolerant energy storage device multiport DC–DC converters

Introduction

In the era, where traditional energy generation and distribution are being replaced with renewable-based hybrid generation and distribution techniques, power electronic converters are playing a crucial role. The converters that interface the energy resources integrated with an energy storage device (ESD) and connected to the load are gaining popularity. The damage to the environment by traditional generation units is one of the main reasons for the new technological advancements related to renewable resources and their management. A recent guideline of the European Union suggests that carbon emissions must be reduced by about 70%–80% in the coming couple of decades. This can be made possible only by considering distributed energy resources on a large scale for the advantages they have regarding their abundant availability and zero level of harmful emissions (Abdolrasol et al., 2022; Allehyani, 2021). Therefore, significant research is being carried out to emphasize the usage of natural energy resources like solar photovoltaics (Abdolrasol et al., 2023; Singh et al., 2020); fuel cells (Das et al., 2022; Samadhiya et al., 2022; Wu et al., 2022), wind turbines, etc. (Farooq et al., 2022; Hussain et al., 2020; Singh et al., 2021). It is evident that the unpredictable power generation using some of these sources enforces the system to include an ESD such as an ESD or an ultracapacitor (Chappa et al., 2024; Latif et al., 2021; Mahafzah et al., 2022; Mishra et al., 2024). Such hybrid sources integrated into a single system have more advantages than conventional power systems like continuous supply, pollution-free, abundant availability of fuel, remote area installations, etc. In such hybrid systems, due to the continuous operation of the system, the semiconductor devices and other components undergo high stress, which leads to the failure of the respective component. This results in either increased demand on other sources or a shutdown of the complete system. In this context, the creation of systems impervious to faults becomes imperative to ensure continuous generation and heightened reliability of the overall system.

The block diagram representing the flow of operation in a fault-tolerant DC–DC converter is depicted in Figure 1. The process involves two stages, that is, fault-diagnosis and fault-compensation. The fault diagnosis is the stage of detecting the faults and its location. Fault compensation is the stage of implementing the corresponding switching strategy to continue the operation of topology similar to prefault without interruption in power supply.

Figure 1.

Block diagram representing the operation of fault-tolerant converter.

Mostly, the faults that occur in such systems lead to the failure of the converter's normal operation. Generally, a DC–DC converter is susceptible to various types of component failures. Among these, semiconductor device faults and capacitor faults stand out as the most prominent. According to Kumar and Elangovan (2020), nearly 34% of faults among the various components in a topology are attributed to semiconductor devices. This is primarily due to heightened stress during the energy conversion process. These faults are mainly classified into Open Circuit (OC) Faults and Short Circuit (SC) Faults. The primary cause of Open Circuit Failure (OCF) in a semiconductor device is driver failures, while Short Circuit Failure (SCF) typically arises from either overstress or excessive usage of switches (Khan and Wen, 2021).

This work presents the performance analysis of two innovative fault-tolerant topologies that are capable of addressing single and multiple-switch faults, thereby mitigating the limitations such as multiple switch fault-tolerance, regulated voltage during postfault operation, uninterrupted power supply, ability to handle both OC and SC faults, more components for reconfiguration, etc. (Ahmad et al., 2021; Emamalipour and Lam, 2022; Huang et al., 2021; Razani and Mohamed, 2021; Siouane et al., 2019; Soon et al., 2020; Wang et al., 2021; Xu et al., 2021).

The presented topologies hold applicability across various domains, including DC microgrids, alternative energy harvesting systems, standalone power plants for domestic loads, and more. Several fault detection algorithms have been reported, leveraging current and voltage sensor data (Bento and Cardoso, 2019; Kim et al., 2019; Zhuang et al., 2021). Consequently, this article's focus is solely on multiple switch fault-tolerant operations and their performance evaluation using various attributes, excluding fault detection. In general, attributes such as stress, losses, reliability, and cost analysis contribute to assessing the performance of converters. Effective maintenance of converter components to operate with minimum stress and losses improves the life of the converter. Proper design of fault-tolerance switching sequence also ensures better reliability of the converters. These performance indices help in sorting the feasibility of the converter being operated for certain applications as per demand. Many fault-tolerant converters proposed have been validated with respect to regulated and stable outputs. However, a combined study of advantages and limitations with respect to performance attributes will help in determining the superiority of converters for any specific application.

The study and analysis in this article have been organized as follows: the fault-tolerant topologies section discusses the operation of the two fault-tolerant topologies with respect to different scenarios of single and multiple switch faults, followed by validation through experimental results with detailed analysis in the results and discussion section. The performance analysis, including stress, losses, reliability, sensitivity and cost, has been discussed in the performance analysis of fault-tolerant topologies section. A quantitative comparison has been presented in the comparative analysis section, followed by the concluding remarks in the conclusion section.

Fault-tolerant topologies

The conventional power conversion system with an ESD for renewable energy applications consists of a two-stage converter (boost and charging/discharging DC–DC converter). To make this OC fault tolerant on a single switch, the diode is relocated as discussed in (Kim et al., 2019). However, the topology discussed cannot handle multiple switches and SC faults. In this regard, two fault-tolerant topologies have been presented in this section that can handle multiple switch faults and both OC and SC switch faults.

Fault-tolerant topology-I

A fault-tolerant topology-I (FTT1) is presented in Figure 2 that can be incorporated in renewable energy-based hybrid systems (Pedapati and Chander, 2022). The system topology comprises a boost converter and a bidirectional converter for ESD charging/discharging. Components S₁, L₁, and D configure the boost converter, and S₂, S₃, and L₂ for bidirectional conversion. S₄ and S₅ serve as bidirectional switches for fault tolerance. This design ensures robust ESD protection with integrated fault-tolerant features. The switching sequence of FTT1 for various fault cases is shown in Figure 3. The operating paths for simultaneous multiple switch faults on S₁ and S₂ and S₂ and S₃ have been depicted in Table 1. In the scenario where a fault occurs on switches S₁ and S₃, it's important to highlight a significant limitation of the current topology: the inability to reconfigure the return path for boost operation using any of the existing switches. This limitation underscores the topology's incompleteness in terms of fault tolerance. To tackle this challenge, a novel topology has been presented in the following section, aiming to surmount this particular limitation.

Figure 2.

Schematic of FTT1 (Pedapati and Chander, 2022).

Figure 3.

Switching sequence of FTT1 (a) Normal condition (b) Switch fault—S₁ (c) Switch fault—S₂ (d) Switch fault—S₃ (e) Simultaneous switch fault—S₁–S₂ (f) Simultaneous switch fault—S₂–S₃.

Table 1.

Paths for multiport converter FTT1 and FTT2 operation during single and multiple switch faults.

FTT	Fault	Case	Fault on		L₁ charging/discharging	Battery charging	Battery discharging
FTT1 and FTT2	No	(i)	No	dT_s	+V_dc − L₁ – S₁ – −V_dc	+V_dc – L₁ – S₂ – L₂ – V_b – −V_dc	+V_b – L₂ – S₃ – −V_b
	No	(i)	No	(1 − d)T_s	+V_dc – L₁ – D – V₀ – −V_dc	−V_b – S₃D – L₂ – +V_b	+V_b – L₂ – S₂D – D – V₀ – −V_b
	Single	(ii)	S₁	dT_s	+V_dc – L₁ – S₂ – S₃ – −V_dc	+V_dc – L₁ – S₂ – L₂ – V_b – −V_dc	+V_b – L₂ – S₃ – −V_b
		(ii)	S₁	(1 − d)T_s	+V_dc – L₁ – D – V₀ – −V_dc	−V_b – S₃D – L₂ – +V_b	+V_b – L₂ – S₂D – D – V₀ – −V_b
		(iii)	S₂	dT_s	+V_dc – L₁ – S₁ – −V_dc	+V_dc – L₁ – S₄ – S₅D – L₂ – V_b – −V_dc	+V_b – L₂ – S3 – −V_b
		(iii)	S₂	(1 − d)T_s	+V_dc – L₁ – D – V₀ – −V_dc	−V_b – S₃D – L₂ – +V_b	+V_b – L₂ – S₅ – S₄D – D – V₀ – −V_b
		(iv)	S₃	dT_s	+V_dc – L₁ – S₁ – −V_dc	+V_dc – L₁ – S₂ – L₂ – V_b – −V_dc	+V_b – L₂ – S₅ – S₄D – S₁ – −V_b
		(iv)	S₃	(1 − d)T_s	+V_dc – L₁ – D – V₀ – −V_dc	−V_b – S₁D – S₂ – L₂ – +V_b	+V_b – L₂ – S₅ – S₄D – D – V₀ – −V_b
	Multiple	(v)	S₁–S₂	dT_s	+V_dc – L₁ – S₄ – S₅D – S₃ – −V_dc	+V_dc – L₁ – S₄ – S₅D – L₂ – V_b – −V_d	+V_b – L₂ – S₃ – −V_b
		(v)	S₁–S₂	(1 − d)T_s	+V_dc – L₁ – D – V₀ – −V_dc	−V_b – S₃D – L₂ – +V_b	+V_b – L₂ – S₅ – S₄D – D – V₀ – −V_b
		(vi)	S₂–S₃	dT_s	+V_dc – L₁ – S₁ – −V_dc	+V_dc – L₁ – S₄ – S₅D – L₂ – V_b – −V_dc	+V_b – L₂ – S₅ – S₄D – S₁ – −V_b
		(vi)	S₂–S₃	(1 − d)T_s	+V_dc – L₁ – D – V₀ – −V_dc	−V_b – S₁D – S₄ – S₅D – L₂ – +V_b	+V_b – L₂ – S₅ – S₄D – D – V₀ – −V_b
FTT2		(vii)	S₁–S₃	dT_s	+V_dc – L₁ – S₂ – S₆ – −V_dc	+V_dc – L₁ – S₂ – L₂ – V_b – −V_dc	+V_b – L₂ – S₆ – −V_b
		(vii)	S₁–S₃	(1 − d)T_s	+V_dc – L₁ – D – V₀ – −V_dc	−V_b – S₆D – L₂ – +V_b	+V_b – L₂ – S₅ – S₄D – D – V₀ – −V_b
		(viii)	S₁–S₂–S₃	dT_s	+V_dc – L₁ – S₄ – S₅D – S₆ – −V_dc	+V_dc – L₁ – S₄ – S₅D – L₂ – V_b – −V_dc	+V_b – L₂ – S₆ – −V_b
		(viii)	S₁–S₂–S₃	(1 − d)T_s	+V_dc – L₁ – D – V₀ – −V_dc	−V_b – S₆D – L₂ – +V_b	+V_b – L₂ – S₅ – S₄D – D – V₀ – −V_b

FTT1: fault-tolerant topology-I; FTT2: fault-tolerant topology-II.

*S_iD denotes the body diode of switch i.

Fault tolerant topology-II

Figure 4 illustrates the fault-tolerant topology-II (FTT2) (Pedapati and Hemachander, 2023). To enhance fault tolerance in FTT1 and address the issue of multiple switch faults occurring on switches S₁ and S₃ and S₁, S₂ and S₃, an additional switch S₆, is introduced in parallel to S₃. This addition aims to provide redundancy and improve the system's resilience. This gives the added advantage of providing a return path under the S₁–S₃ fault condition, making it completely fault-tolerant. FTT2 operates similarly to the previous topology, FTT1, in handling single switch faults on S₁, S₂, and S₃ individually, as well as multiple switch faults on S₁–S₂ and S₂–S₃. However, FTT2 also addresses other scenarios involving multiple switch faults that were not covered by FTT1. This expanded fault tolerance capability enhances the robustness of the system in various fault scenarios, ensuring reliable operation even under adverse conditions. The same has been discussed below with the help of Figure 5 and Table 1.

Figure 4.

Schematic of FTT2 (Pedapati and Hemachander, 2023).

Figure 5.

Switching diagrams of FTT2 (a) Simultaneous switch fault—S₁–S₃ (b) Simultaneous switch fault—S₁–S₂–S₃.

During simultaneous fault on multiple switches S₁ and S₃ and S₁, S₂_, and S₃, the redundant path for boost operation is provided as shown in Figure 5(a) and (b) respectively. The operating paths for the same have been presented in Table 1. An alternate redundant path for simultaneous switch fault on S₁ and S₃ can also be provided through the switches S₃, S₄ and S₅, however, at the cost of increased voltage drop. Hence, it is clear that FTT2 surpasses FTT1 due to its features such as complete fault tolerance, consistent output voltage, continuous operation, and enhanced reliability.

Steady state operation

Utilizing the switching sequence outlined in Figures 3 and 5, the steady-state analysis of the proposed FTC has been tabulated as shown in Table 2. It can be observed that the switching sequence is compensated for fault scenarios to maintain the boost mode when the ESD is idle, buck mode to charge the ESD and boost mode to discharge the ESD.

Table 2.

Steady state analysis for FTT1 and FTT2.

Fault case	Duration	Idle mode of ESD	Charging mode of ESD	Discharging mode of ESD
No fault, S₁, S₂, S₃	d₁	V_L1 = V_dc	V_L2 = V_b	V_L2 = V_b
	d₂–d₁	V_L1 = V_dc – V₀	V_L2 = V_dc – V_L1 – V_b	V_L2 = V_b
	1–d₂	V_L1 = V_dc – V₀	V_L2 = V_b	V_L2 = V_b – V₀
S₁–S₂, S₂–S₃, S₁–S₃	d₁	V_L1 = V_dc	–	V_L2 = V_b
	d₂–d₁	V_L1 = V_dc – V₀	V_L2 = V_dc – V_L1 – V_b	V_L2 = V_b
	1–d₂	V_L1 = V_dc – V₀	V_L2 = V_b	V_L2 = V_b – V₀
Gain	T_s	$\frac{V_{0}}{V_{d c}} = \frac{1}{1 - d_{1}}$	$\frac{V_{b}}{V_{d c}} = d_{2} - d_{1}$	$\frac{V_{0}}{V_{b}} = \frac{1}{1 - d_{2}}$

FTT1: fault-tolerant topology-I; FTT2: fault-tolerant topology-II; ESD: energy storage device.

Filter components have been designed using,

L_{1} = \frac{{(1 - d_{1})}^{2} d_{1} R_{L}}{2 f_{s}} and L_{2} = \frac{{(1 - d_{2})}^{2} d_{2} R_{L}}{2 f_{s}}

(1)

C = \frac{d_{1}}{R_{L} f_{s} (\frac{Δ V_{0}}{V_{0}})}

(2)

Results and discussion

The performance of the fault-tolerant topologies discussed in the previous section has been validated in real-time under different operating scenarios on the developed laboratory prototype shown in Figure 6. The circuit specifications and operational parameters have been taken into account in accordance with Table 3. The controller onboard is Xilinx Spartan-6 XC6SLX9 FPGA in a TQG144 package with 90KB RAM and two clock management tiles operating at clock frequency of 100 MHz. It has 34 header pins used for SPM Interface and 40 header pins for External Interface which includes six PWM pins, 37 I/O pins, and four capture pins. A 4-channel 12-bit I2C-based ADC and 1-channel DAC are also a part of TQG144 package. The filter components were determined through equations (1) and (2) (Erickson and Robert, 2001). A rapid-response fuse is linked in series with the switches to disrupt the circuit in the event of an SC fault occurring on the switch, effectively treating it as an open-circuit fault. In case of an OC fault, the switch however acts as an open circuit. The corresponding switching sequences have been employed immediately after the switch faults so as to deliver uninterrupted output voltage. The experiments have been conducted and results have been presented for all combinations of switch faults discussed in the fault-tolerant topologies section. There have been many fault detection algorithms reported based on passive component's measurements (Bento and Cardoso, 2019; Kim et al., 2019; Zhuang et al., 2021). Hence, the focus of this article is only on fault-tolerant operations and not on fault detection. Figure 7(a) shows the real-time results of FTT1 during the transition from charging mode to discharging mode of the ESD. The topology ensures that the output voltage remains stable at 110 V during the transition from charging to the alternative ESD mode. This shift in ESD operational mode can be identified by the alteration of ESD current (I_L2) from positive to negative value. The equivalent change in input current (I_L1) can also be observed. The experimental results of FTT1 operating in the charging mode of ESD during a switch fault on S₁ are presented in Figure 7(b). The change in ESD current can be observed as the switching strategy employed utilizes the same switch S₂ for both voltage regulation and charging of ESD. During the fault on switch S₂ while charging the ESD, the switching strategy employed reconfigures the circuit to provide an alternate path for the current using an auxiliary switch, and hence no major change has been observed in V₀, I_L1_, and I_L2 as shown in Figure 7(c). Figure 7(d) illustrates the experimental outcome of FTT1 in the event of a single switch fault occurring on switch S₃ during the discharging phase of ESD.

Figure 6.

Photograph of laboratory prototype of fault-tolerant topologies.

Figure 7.

Experimental results of FTT1 (a) Charging mode to discharging mode—no-fault (b) Charging mode—fault on S₁ (c) Charging mode—fault on S₂ (d) Discharging mode—fault on S₃ (e) Charging mode—sequential fault on S₁ and S₂ (f) Discharging mode—sequential fault on S₂ and S₃.

Table 3.

Specifications used for laboratory prototype.

Parameter	Value/specification
Power rating P₀	700 W
Input DC voltage V_dc	72 V
Output DC voltage V₀	110 V
Nominal ESD voltage, V_b	60 V
Switching frequency, f_s	25 kHz
Controller onboard	Spartan-6, FPGA-based
Capacitor C	470 µF, 450 V
Load resistance, R_L	20 Ω
Inductors, L₁, L₂	2 mH

ESD: energy storage device.

The experimental results of FTT1 operated during a sequential switch fault on S₁–S₂ in the charging mode of ESD as shown in Figure 7(e). The result shows that the regulated load voltage is achieved with a ripple of less than 10% during postfault operation. However, it is observed that the charging current has been reduced since the switch S₃ has been shared for both boost and charging operations, limiting the feasibility of maintaining different duty ratios. Similar empirical results are shown in Figure 7(f), for ESD for discharging mode during simultaneous faults on switches S₂–S₃.

As mentioned previously, the switching sequence utilized in FTT2 for individual switch faults on S₁, S₂, or S₃ mirrors that of FTT1. Consequently, the outcomes obtained align closely with those depicted in Figure 7. The operating procedure of FTT2 during multiple switch faults on S₁–S₂ and S₂–S₃ is similar to that of FTT1. To overcome the limitation of FTT1 concerning the return path for multiple switch faults in switches S₁ and S₃, the topology has been reconfigured with a redundant switch S₆. Accordingly, the experimental results presented in Figure 8(a), ensure the fault-tolerance capability of FTT2 for multiple switch faults on switches S₁ and S₃ occurring sequentially. The redundant switch also enables FTT2 topology to handle multiple switch faults on switches S₁, S₂ and S₃. The same has been validated with the results presented in Figure 8(b) and 8(c) during both the charging and discharging modes of ESD, respectively. It has been observed that the output voltage is regulated for various multiple switch fault scenarios.

Figure 8.

Experimental results of FTT2 (a) Discharging mode—sequential fault on S₁ and S₃ (b) Charging mode—sequential fault on S₁, S₂, and S₃ (c) Discharging mode—sequential fault on S₁, S₂, and S₃.

The findings showcased confirm the efficacy of FTT2 in managing more than one simultaneous switch fault while maintaining a regulated output voltage. This demonstrates its capability to handle various types of switch faults across both ESD operating modes, all while boasting fewer components and enhanced reliability.

Performance analysis of fault-tolerant topologies

Stress analysis

Ensuring that each switch is adequately stressed is a critical consideration when designing fault-tolerant converters. Since this article deals with the fault tolerance of switches, the stress analysis has been addressed only on the semiconductor devices considered to be under the influence of faults. Selection of suitable semiconductor devices while in the design phase will enhance the performance of the system to a greater extent. This selection is easy when the stress analysis of the converter is handy. The stress can be different depending on the state of operation of switches (on-state and off-state). This stress on switches can be classified into two types: (i) Voltage Stress and (ii) Current Stress (Sahu et al., 2019).

Voltage stress

The voltage blocked by a switch during its off-state is referred to as the voltage stress on the switch. This has been analyzed for the topologies shown in Figures 2 and 4. The maximum voltage blocked by switch S₁ can be depicted as $V_{d c} - V_{L 1} .$ The operation discussed in previous sections clarifies that S₂ and S₃ are operated according to the requirement of ESS to be charged or discharged. Hence, while charging the ESD, the maximum voltage across the switch S₂ during the off-state is $V_{d c} - V_{L 1} - V_{L 2} - V_{b}$ and while discharging the ESD, the maximum voltage blocked by the switch S₃ can be depicted as $V_{L 2} - V_{b}$ . The voltage stress on the diode in the topologies can be determined by the maximum voltage blocked by diode D during its off-state and is given by $V_{0}$ . The same has been reproduced in Table 4.

Table 4.

Current and voltage stress on semiconductors of reported topologies.

Topology	Device	Voltage stress	Current stress
FTT1 and FTT2	S₁	V_dc – V_L1	max(I_L1)
	S₂/S₄	V_dc – V_L1 – V_L2 – V_b	max(I_L2)
	S₃/S₅	V_L2 – V_b	max(I_L2)
	D	V₀	max(I_L1 + I_L2)
FTT2	S₆	V_L2 – V_b	max(I_L2)

FTT1: fault-tolerant topology-I; FTT2: fault-tolerant topology-II.

Current stress

The maximum possible current passing through the switch during its on-state is referred to as the current stress on that switch. For the topologies in Figures 2 and 4, the maximum current flowing through each switch is evaluated as $\max (I_{L 1})$ , $\max (I_{L 2})$ and $\max (I_{L 2})$ on S₁, S₂ and S₃ respectively. It is worth noting that the inductor's current $I_{L 2}$ in switches S₂ and S₃ happen to have current stress only during the operating modes of ESD, respectively. Similarly, the maximum current in the diode D is equal to $\max (I_{L 1} + I_{L 2})$ during the charging of ESD and $\max (I_{L 1} - I_{L 2})$ during the discharging of ESD. The selection of proper current and voltage-rated switches can be made easy with this analysis. This also improves the reliability of the system. Also, selecting the switches with appropriate current and voltage ratings along with low on-state resistance will improve the efficiency of the converter by decreasing the conduction losses across the semiconductor devices. The same has been reproduced in Table 4. The quantitative comparison of current and voltage stress on semiconductors of FTT1 and FTT2 is depicted in Table 5.

Table 5.

Quantitative comparison of current and voltage stress on semiconductors of FTT1 and FTT2.

Component	FTT1		FTT2
Component	Vmax (V)	Imax (A)	Vmax (V)	Imax (A)
S₁	118	8.60	118	8.60
S₂	118	6.45	118	6.45
S₃	118	6.45	118	6.45
S₄	118	6.45	118	6.45
S₅	118	6.45	118	6.45
S₆	–	–	118	6.45
D	110	4.95	110	4.95

FTT1: fault-tolerant topology-I; FTT2: fault-tolerant topology-II.

Losses and efficiency

It is a well-established fact that a converter is recognized for real-time industrial implementation depending on how high the converter's efficiency can be when operated in different scenarios. Hence, the losses and efficiency analysis has been evaluated for both the topologies. In power electronic converters, a significant portion of the total loss arises from conduction and switching losses, which collectively represent the overall loss of the component (Ustun and Mekhilef, 2010). The conduction losses $(P^{c o n})$ for the presented topologies are evaluated for the switches, diode, inductor, and capacitor. This loss in a switch is found using the on-state resistance, the forward voltage drops and conduction resistance for a diode, and equivalent series resistances (internal) for an inductor and a capacitor. The total conduction loss is given by

P^{c o n} = \sum_{i = 1}^{n} P_{S C_{i}} + P_{D C} + P_{C} + P_{L}

(3)

where P_SCi is the conduction loss of the ith switch, P_DC is the conduction loss of the diode, P_c is the loss in the capacitor, and P_L is the loss in the inductor. The switching loss

(P^{s w})

, however, is concerned with the switch and diode only. It is the loss produced in the converter during the turn-on and turn-off process of the switches and diodes. It can be calculated for each and every individual component based on the turn-on and turn-off energy losses (generally available in the component datasheet).

P^{s w} = \sum_{i = 1}^{n} P_{S W_{i}} + P_{D W}

(4)

where P_swi is the switching loss in the switch and P_DW is the switching loss in the diode. Then, the total loss in the converter is given by

P^{L o s s} = P^{c o n} + P^{s w}

(5)

For the topologies discussed, the same has been studied and tabulated for various operating scenarios. The losses for all the components have been determined empirically, and the efficiency for both the topologies has been evaluated considering different modes of operation of ESD with respect to various switch fault case scenarios. Figure 9 presents the loss distribution analysis for all components of FTT1. The component specifications considered for this analysis are shown in Table 2. P_L1 and P_L2 are the losses in inductors L₁ and L₂_, respectively, P_C is the loss in the capacitor, P_D is the loss in the diode, P_S is the total loss in the switches. Similarly, the loss distribution analysis for FTT2 has also been shown in Figure 10. It is to be noted that the loss percentages shown in Figures 11 and 12 are the average losses considering all possible combinations of switch faults. From the losses presented, it can be observed that the average switching loss in FTT2 is increased by 4% compared to FTT1 due to the extra switch S₆. In addition, it is observed that the combined passive component loss (P_L1 and P_L2) and filter component loss (P_c) are almost constant in both FTT1 and FTT2. Hence, it can be concluded that the complete fault-tolerant ability has been achieved by FTT2 by adding an extra switch (S₆) in FTT1 without significant variation in overall loss.

Figure 9.

Component wise loss distribution analysis of FTT1.

Figure 10.

Component-wise loss distribution analysis of FTT2.

Figure 11.

Comparison of efficiencies among the FTT1 and FTT2 during charging mode of ESD in all operating cases.

Figure 12.

Comparison of efficiencies among the FTT1 and FTT2 during discharging mode of ESD in all operating cases.

In the loss analysis, efficiency is computed using equations (6) and (7) for charging and discharging modes of ESD, where P_B is the power consumed/delivered by ESD, P₀ is the output power and P_IN is the input power from the source. Figures 11 and 12 display efficiency comparisons between FTT1 and FTT2 across various possible combinations of switch faults during different operating modes of ESD. It can be observed that the efficiencies of topologies FTT1 and FTT2 are same for no-fault, fault on switches S₁, S₂, S₃, S₁–S₂, S₂–S₃ as the operating paths are same. However, as FTT1 fails to operate during S₁–S₃ and S₁–S₂–S₃ switch fault scenarios, only FTT2 efficiencies have been reported.

% η_{c} = \frac{(P_{O} + P_{B})}{P_{I N}} \times 100 = \frac{P_{O}}{(P_{0} + L o s s e s)} \times 100

(6)

% η_{d} = \frac{P_{O}}{(P_{I N} + P_{B})} \times 100 = \frac{P_{O}}{(P_{0} + L o s s e s)} \times 100

(7)

Reliability analysis

This section addresses the performance analysis with respect to reliability for the topologies, FTT1 and FTT2. The reliability analysis has been conducted utilizing the Markov Reliability Assessment Approach (MRAA) for both the established and FTTs discussed in previous sections. This approach determines the mean-time-to/between-failure (MTTF) profile of the converter by employing directed graphs to comprehend the probability of transitioning from one state to another. In this article, the states are defined by the potential number of switch faults within the topology and the directed graph is constructed to illustrate the likelihood of transitioning between various finite possibilities. Figure 13 depicts the reliability model of the Markov Chain applied to both existing and present converters, illustrating the number of switch faults across five states and ten possible state transitions. The reliability of different fault-tolerant converter topologies has been investigated using the MRAA in (Emamalipour and Lam, 2022; Kumar et al., 2022; Tarzamni et al., 2021). In this study, the reliability analysis encompasses five states: (1) Healthy: All switches and components are operational, (2) Single Switch Fault: One of the switches designated for fault tolerance experiences a fault, (3) Two Switch Fault: Two of the switches designated for fault tolerance experience faults, (4) Three Switch Fault: All switches designated for fault tolerance experience faults, (5) Absorbing: One of the redundant switches or components experiences a fault, leading to complete converter failure. The standard failure rates of each component have been assessed utilizing the military handbook MIL-HDBK-217F (n.d.). The failure rates $δ_{C}$ , $δ_{S}$ , $δ_{L}$ , $δ_{D}$ mentioned in the analysis associated with capacitor, switch, inductor and diode, respectively.

Figure 13.

Reliability model of fault-tolerant converters based on Markov Chain.

Figure 14.

Reliability comparison among (Kim et al., 2019) and converters FTT1 and FTT2.

Figure 15.

Reliability profile comparison with the change in a_s.

The failure rates of components are affected by various factors including electrolytic capacitors (μ_C), environmental conditions (μ_E), application specifics (μ_A), quality standards (μ_Q), voltage stress in capacitors and diodes (μ_v and μ_s), temperature variations (μ_T), and the base failure rate of each component $(δ_{b})$ .

Transition probabilities between states are depicted in a matrix, with dimensions determined by the number of states considered. However, only the feasible states maintain nonzero values in the matrix. Let's denote the probability of a state as Q_n(t), where “n” signifies the specific state for which the probability is defined. All probabilities can be expressed using the following relationship.

\frac{d}{d t} [Q_{1} (t) \dots Q_{5} (t)] = [Q_{1} (t) \dots Q_{5} (t)] \times [\begin{matrix} a & b \\ c & d \end{matrix}]

(8)

where

a = [\begin{matrix} δ_{11} & δ_{12} & δ_{13} \\ δ_{21} & δ_{22} & δ_{23} \\ δ_{31} & δ_{32} & δ_{33} \end{matrix}] b = [\begin{matrix} δ_{14} & δ_{15} \\ δ_{24} & δ_{24} \\ δ_{34} & δ_{34} \end{matrix}]

c = [\begin{matrix} δ_{41} & δ_{42} & δ_{43} \\ δ_{51} & δ_{52} & δ_{53} \end{matrix}] d = [\begin{matrix} δ_{44} & δ_{45} \\ δ_{54} & δ_{55} \end{matrix}]

(9)

In a MRAA illustrating an FTT, where the states represent fault scenarios, it's apparent that reverting from one state to a previous one is not feasible. Therefore, the entries representing the reverse transition in the transition matrix can be substituted with nulls.

i . e . δ_{21} = δ_{31} = δ_{32} = δ_{41} = δ_{42} = δ_{43} = δ_{51} = δ_{52} = δ_{53} = δ_{54} = 0

(10)

Furthermore, the diagonal elements $δ_{11}, δ_{22}, δ_{33}, δ_{44}, δ_{55}$ are determined as the negative sum of all other probabilities of state transition values associated with that specific state. That is

δ_{11} = - (δ_{12} + δ_{13} + δ_{14} + δ_{15})

δ_{22} = - (δ_{23} + δ_{24} + δ_{25})

δ_{33} = - (δ_{34} + δ_{35})

δ_{44} = - δ_{45}

δ_{55} = 0

(11)

Given that State-1 from Figure 13 represents a healthy state while the others signify faulty states, the preliminary status for the probability vector can be assumed as follows:

Q_{n} (0) = [1 0 0 0 0]

(12)

Utilizing the aforementioned equations, the reliability of the FTTs can be computed as

R = Q_{1} (t) + Q_{2} (t) + Q_{3} (t) + Q_{4} (t) + Q_{5} (t)

(13)

The reliability depiction of the FTT1 and FTT2 typically involves a study centered on the failure rates of its components, as indicated in Table 6. However, it is crucial to consider certain factors affecting the failure rates of different components, especially when dealing with sensitive converters. In the topology reported in Kim et al. (2019), operation is confined to one switch fault only, thus neglecting transition paths involving states 3 and 4. Additionally, the failure rate for the transition path from state 1 to 2 (i.e. $δ_{12}$ ) is calculated concerning the singular switch addressed for fault. Similar methodology has been applied to the two topologies, FFT1 and FTT2, and their respective computations for transition paths are presented in Table 7, where R₀, R₁, and R₂ denote the failure rates of (Kim et al., 2019) FTT1 and FTT2, respectively. Figure 1 4 illustrates the comparison of reliability profiles between the existing topology and the topologies FTT1 and FTT2. The reliability profile of FTT2 demonstrates a significantly longer era compared to FTT1 and the topology discussed in Kim et al. (2019). In addition, adding a redundant switch to FTT1 has resulted in an improvement in the reliability of FTT2. This offers a resolution for industrial applications prioritizing reliability over the economic aspects of the topology. Furthermore, Figure 1 5 depicts the reliability profiles of the converter in Kim et al. (2019) and the presented topologies FTT1 and FTT2 concerning the probability of SCF (a_s) of the switch over time. Notably, the reliability profile of FTT2 concerning the probability of SCF is much more stable than the others and is not converging to 0 even at million hours. However, the reliability profiles of topology in Kim et al. (2019) and FTT1 converged to 0 before a million hours. This indicates that FTT2 is comparatively more reliable with respect to any type of switch fault. The comparison concerning operating temperature is depicted in Figure 16. From the findings, a clear demonstration of superior reliability of FTT2 is observed. It indicates a much longer lifetime under operating temperatures within 25°–150° over the existing topology and FTT1 under various operating scenarios.

Figure 16.

Reliability profile comparison with the change in T_a.

Table 6.

Component failure rate.

S No.	Elements	Failure rate (Ꞙ)	Value
1	Switches (S)	$δ$ _S = $δ$ _b. μ_T. μ_A. μ_Q. μ_E	$δ$ _S = 1.131054
2	Diode (D)	$δ$ _D = $δ$ _b. μ_T. μ_S. μ_C. μ_Q. μ_E	$δ$ _D = 0.069924
3	Inductor (L₁, L₂)	$δ$ _L = $δ$ _b. μ_T. μ_Q. μ_E	$δ$ _L1 = 0.0009694
3	Inductor (L₁, L₂)	$δ$ _L = $δ$ _b. μ_T. μ_Q. μ_E	$δ$ _L2 = 0.0005473
4	Capacitor (C)	$δ$ _C = $δ$ _b. μ_T. μ_C. μ_V. μ_Q. μ_E	$δ$ _C = 0.0001806

Table 7.

Reliability profile parameters.

Topology	Paths for transition	MTTF (hrs/failure)
(Kim et al., 2019)	$δ$ ₁₂ = 0.565; $δ$ ₁₃ = 0; $δ$ ₁₄ = 0; $δ$ ₁₅ = 3.426; $δ$ ₂₃ = 0; $δ$ ₂₄ = 0; $δ$ ₂₅ = 1.206; $δ$ ₃₄ = 0; $δ$ ₃₅ = 0; $δ$ ₄₅ = 0	$M T T F = \int_{0}^{\infty} R_{0} (t) d t = 0.31509 \times 10^{6}$
FTT1	$δ$ ₁₂ = 1.665; $δ$ ₁₃ = 3.330; $δ$ ₁₄ = 0; $δ$ ₁₅ = 3.426; $δ$ ₂₃ = 1.110; $δ$ ₂₄ = 0; $δ$ ₂₅ = 1.206; $δ$ ₃₄ = 0; $δ$ ₃₅ = 0.651; $δ$ ₄₅ = 0	$M T T F = \int_{0}^{\infty} R_{1} (t) d t = 0.49669 \times 10^{6}$
FTT2	$δ$ ₁₂ = 1.6965; $δ$ ₁₃ = 3.3930; $δ$ ₁₄ = 3.3930; $δ$ ₁₅ = 1.7661; $δ$ ₂₃ = 1.1310; $δ$ ₂₄ = 1.1310; $δ$ ₂₅ = 3.4626; $δ$ ₃₄ = 0.5655; $δ$ ₃₅ = 1.2006; $δ$ ₄₅ = 0.651	$M T T F = \int_{0}^{\infty} R_{2} (t) d t = 0.57633 \times 10^{6}$

FTT1: fault-tolerant topology-I; FTT2: fault-tolerant topology-II; MTTF: mean-time-to/between-failure.

Cost analysis

This section deals with the investigation of the cost involved for both topologies, FTT1 and FTT2 based on their resiliencies. Any power converter's total cost includes capital, maintenance, and power loss costs. The capital cost is calculated based on the components used in the converter. For FTT1 and FTT2, the capital cost depends on the inductors, capacitors, semiconductor switches, and diode. As per Mouser (n.d.), the cost of components per item would be ₹208.33 for the inductor, ₹65.52 for the capacitor, ₹119.52 for the semiconductor switch, ₹10.22 for the diode. Hence, the capital cost for FTT1 and FTT2 can be obtained as:

C_{c a p} = k * 119.52 + 1 * 10.22 + 2 * 208.33 + 1 * 65.52 + C_{c o n t}

(14)

where k is the total number of switches used in the converter and C_cont is the cost of the controller used for implementing the topology's switching sequence as per the discussed fault-tolerant strategy.

Since the fault-tolerant strategy implemented is a reconfigurable type, the maintenance cost is expected to be minimal as it has no downtime period. Hence, the financial loss incurred during the operation can be neglected. However, for Y years of lifetime, the maintenance cost can be deduced based on the reliability of the converter as follows:

C_{m a i n t} = \frac{Y}{M T T F_{F T T}} * C_{c a p}

(15)

In addition, a power loss cost can be assumed to be around ₹0.5/kWh. Hence, a total power loss cost for a year can be calculated as

C_{P L} = D_{p} * 0.5 * 8760

(16)

where D_p is the power dissipation of the topology.

Using the equations (14)–(16), the total cost involved for the converter can be computed as:

C_{T o t a l} = C_{c a p} + C_{m a i n t} + C_{P L}

(17)

Tables 8 and 9 show the total cost of the converters for a lifetime of 15 years and 30 years respectively. The tabulation in Table 8 deduces that the total cost of a converter with an expected lifetime of 15 years for Kim et al. (2019) is ₹2944.10, FTT1 is ₹2992.45, and FTT2 is ₹2989.22. Similarly, Table 9 shows that for an expected lifetime of 30 years, the total cost of converters in Kim et al. (2019) is ₹ 44,037.27, FTT1 is ₹3754.89, and FTT2 is ₹3768.93 (Components Costs). It is to be noted that all the converter costs are nearly the same and with the added advantage of being fully fault tolerant for FTT2, this can be an economic choice with better features of reliability, lesser power dissipation, regulated output voltage, single and multiple switch fault handling capability for both OC and SC type of faults.

Table 8.

Total cost of topologies for 15 years of lifetime.

Topology	$C_{c a p}$	$C_{m a i n t}$	$C_{P L}$	$C_{T o t a l}$
(Kim et al., 2019)	1850.96	772.09	321.05	2944.10
FTT1	2090	553.00	279.44	2922.45
FTT2	2209.52	503.76	275.94	2989.22

FTT1: fault-tolerant topology-I; FTT2: fault-tolerant topology-II.

Table 9.

Total cost of topologies for 30 years of lifetime.

Topology	$C_{c a p}$	$C_{m a i n t}$	$C_{P L}$	$C_{T o t a l}$
(Kim et al., 2019)	1850.96	1544.18	642.10	4037.24
FTT1	2090	1106.01	558.88	3754.89
FTT2	2209.52	1007.53	551.88	3768.93

FTT1: fault-tolerant topology-I; FTT2: fault-tolerant topology-II.

Sensitivity analysis

The sensitivity of a power converter is defined as the relative change in the output voltage with respect to any change in the input voltage or any other parameters that affect the operation of the system, such as the duty ratio of the switches. In particular, the sensitivity of the system studied with respect to the duty cycle and input voltage defines the stability of the system. In general, the sensitivity of a variable p with respect to q can be written as

ψ_{p}^{q} = \frac{d p / p}{d q / q} = \frac{d p}{d q} . \frac{q}{p}

(18)

Hence, the sensitivity of system is evaluated for output voltage with respect to input voltage and the duty cycles of switches operated for various modes as discussed in previous sections. In this regard, the sensitivity of the system with respect to different parameters has been tabulated in Table 10.

Table 10.

Sensitivity analysis of reported topologies.

Sensitivity	ESD idle mode	ESD charging mode		ESD discharging
Sensitivity	Load	Load	ESD	Load	ESD
Voltage gain	$V_{0} / V_{i n}$	$V_{0} / V_{i n}$	$V_{b} / V_{i n}$	$V_{0} / V_{i n}$	$V_{0} / V_{b}$
$ψ_{V_{0}}^{V_{i n}}$	1	1	0	1	0
$ψ_{V_{0}}^{d_{1}}$	$\frac{d_{1}}{1 - d_{1}}$	$\frac{d_{1}}{1 - d_{1}}$	0	$\frac{d_{1}}{1 - d_{1}}$	0
$ψ_{V_{0}}^{d_{2}}$	0	0	0	0	$\frac{d_{2}}{1 - d_{2}}$
$ψ_{V_{0}}^{V_{b}}$	0	0	0	0	1
$ψ_{V_{b}}^{V_{0}}$	0	0	1	0	0

ESD: energy storage device.

Comparative analysis

In Table 11, some similar fault-tolerant topologies reported recently have been compared with FTT1 and FTT2. The advantages and limitations have been tabulated individually. As mentioned earlier, the modified boost converter in Kim et al. (2019) have fewer switches to operate. However, it is limited to single switch fault tolerant operation only, that is, on boost switch only. FTT1 has comparatively more switches. However, it can be operated as a fault-tolerant for all single switch faults and two cases of multiple switch faults. The second topology FTT2 has one additional switch compared to FTT1 to overcome the limitation discussed in the fault-tolerant topology-I section. Though this makes the topology completely fault-tolerant, the increased number of switches is still a limitation for this topology. However, the pros of FTT2 regarding the fault tolerance of single and multiple switches, the capability of handling OC/SC fault, regulated output voltage post-switch fault, and uninterrupted supply post-switch fault make it an apt choice for hybrid renewable energy-based applications.

Table 11.

Qualitative and quantitative analysis of fault-tolerant topologies.

Topology		Soon et al. (2020)	Bento and Cardoso (2019)	Kim et al. (2019)	FTT1	FTT2
Number of switches	Normal operation	3 (1 per module)	3	3	3	3
	Redundant/reconfigured	0	0	0	2	3
	Total	3 (1 per module)	3	3	5	6
Fault tolerance	Single switch	S₁, S₂, S₃	S₁, S₂, S₃	S₁	S₁, S₂, S₃	S₁, S₂, S₃
	Multiple switch	No	S₁–S₂, S₂–S₃, S₁–S₃	No	S₁–S₂, S₂–S₃	S₁–S₂, S₂–S₃, S₁–S₃, S₁–S₂–S₃
	Complete FT	No	No	No	No	Yes
Reported maximum efficiency (%)	Normal condition	91.05	NR	92.67	93.62	93.70
Reported maximum efficiency (%)	Faulty condition	90.25	NR	92.71	93.58	93.66
Type of switch faults addressed		OC/SC	OC	OC	OC/SC	OC/SC
Advantages		Simple	Less switches	Fewer switches	Multiple switch FT	Complete FT
Limitations		Not economic, reduced output	Reduced output	Single switch FT only	Not complete FT	More switches

OC: open circuit; SC: short circuit; NR: not reported; FTT1: fault-tolerant topology-I; FTT2: fault-tolerant topology-II.

Conclusion

This article focuses on two reconfigurable multiport converter topologies with fault tolerance operation and their switching strategies, along with their performances for renewable-based hybrid standalone applications to provide an uninterrupted, regulated, efficient, and reliable supply for various probable combinations of switch fault scenarios. The laboratory prototypes for both the topologies, FTT1 and FTT2 have been developed, and the operation of converters with various fault scenarios has been studied and analyzed. The experimental results validate the performance of the reported topologies for a combination of various single and multiple switch fault scenarios. It has been observed that FTT1 is not completely fault-tolerant. Such limitation of FTT1 has been addressed in FTT2. It has been observed that FTT2 provides complete fault tolerance along with regulated output voltage, the capability to handle any type of switch faults, and the power demanded by the load. Further, the performance analysis with respect to losses, stress, reliability, and cost have been studied for both topologies. The empirical findings, performance analysis, and comparison with existing literature collectively suggest the superior effectiveness of FTT2 in renewable-based hybrid standalone applications.

Footnotes

ORCID iD

Taha Selim Ustun

Funding

The author(s) received no financial support for the research, authorship, and/or publication of this article.

Declaration of conflicting interests

The author(s) declared no potential conflicts of interest with respect to the research, authorship, and/or publication of this article.

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Performance analysis of a fault-tolerant multiport converter for hybrid standalone applications

Abstract

Keywords

Introduction

Fault-tolerant topologies

Fault-tolerant topology-I

Fault tolerant topology-II

Steady state operation

Results and discussion

Performance analysis of fault-tolerant topologies

Stress analysis

Voltage stress

Current stress

Losses and efficiency

Reliability analysis

Cost analysis

Sensitivity analysis

Comparative analysis

Conclusion

Footnotes

ORCID iD

Funding

Declaration of conflicting interests

References