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Abstract

In this paper, discrete-event simulation is used to evaluate the performance of a cluster-based hypercube architecture running parallel simplex and parallel Gaussian elimination algorithms.

The cluster-based hypercube architecture enhances the performance of the nodes of the existing hypercube architecture systems by incorporating in each node, a cluster of n execution processors connected through a small cross-bar switch with n memory modules. The memory modules in each node are shared by the processors within the node.

The simulations were developed for both the cluster-based hypercube architecture and the Intel Personal Supercomputer (iPSC/860, a conventional hypercube), and the results obtained were compared. The simulation results show a response time performance improvement of up to 30% in favor of the cluster-based hypercube architecture. We also observe that for increased link delays, the performance gap increases significantly in favor of the cluster-based hypercube architecture.

Keywords

Cluster-based hypercube cross-bar discrete-event simulation

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Simulation Study of the Performance of a Cluster-Based Hypercube Multicomputer

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