Generating Simulation Models from Natural Language Specifications

Abstract

A prototype system for the automatic generation of VHDL simulation models from requirements expressed in natural language is described. Requirements are parsed and analyzed semantically to produce knowledge representations called conceptual graphs. Multiple references (coreferences) to objects (values and devices) are detected among the graphs so they can be integrated into a single graph representing the given requirements. The graph is then searched for behavioral concepts (actions, events and states) and objects (values, devices and carriers) which are translated into VHDL processes and signals or data values. Causal dependencies represented in the graph are used to organize the behavioral information into if-statements. The resulting collection of processes and signal definitions are then formatted into a VHDL entity for simulation. A designer will first need to define any types left unspecified in the requirements. A simple example for a multi-function register is given, and results of experiments generating VHDL models of up to 60 lines from descriptions of up to 10 sentences are tabulated.