Switch-level faults, as opposed to traditional gate-level faults, can more accurately model the physical failures found in the integrated circuit. However, existing fault simulation techniques have a worst-case computational complexity of O(n 2), where n is the number of devices in the circuit. A Parallel Hardware Accelerated Fault Simulator (PHAFS) has been proposed in order to reduce fault simulation complexity to O(L2), where L is the number of levels of switches encountered when traversing the circuit from output to input. This paper presents the VHSIC (Very High Speed Integrated Circuit) hardware description language simulation techniques used to verify the parallel fault simulation algorithm and to verify the algorithm's complexity. This paper also presents predicted speed-up performance results versus partition size for benchnark circuits.
Prathima Agrawal , Vishwani D. Agrawal, Kwang-Ting Cheng, and Raffi Tutundjian, "Fault Simulation in a Pipelined Multiprocessor System," IEEE International Test Conference Proceedings, pp 727 - 734, 1989 .
2.
Ajit Agrawal , and Debashis Bhattacharya, "CMP3F: A High Speed Fault Simulator for the Connection Machine," IEEE International Test Conference Proceedings, pp 410 - 416,1990.
3.
Z. Barzilai , D.K. Beece, L.M. Huismon, V.S. Iyengar, and G.M. Silberman, "SLS-A Fast Switch-level Simulator for Verification and Fault Coverage Analysis," IEEE 23rd Design Automation Conference , pp 164 - 170, 1986.
4.
A. Bataineh , F. Özgüner, and I. Szauter, "Parallel and Vector Logic and Fault Simulation Algorithms on the Cray Y-MP Supercomputer," SIMLILATION , vol 61, no 3, pp 161-169, Sept. 1993.
5.
W.D. Billowitch , VHDL Tech Notes, The VHDL Consulting Group, Bethlehem, PA, June 1990.
6.
A.K. Bose, P. Kozak, C-Y. Lo, H.N. Nham, E. Pacas-Skewes, and K. Wu, "A Fault Simulator for MOS LSI Circuits," IEEE 19th Design Automation Conference Proceedings, pp 400 - 409,1982.
7.
F.Brglez andH. Fujiwara, "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran," Proceedings of the IEEE International Symposium on Circuits and Systems, Kyoto , pp 663-698, June 1985.
8.
Randal E. Bryant , and Michael D. Schuster, "Performance Evaluation of FMOSSIM, a Concurrent Switch-Level Fault Simulator," IEEE 22nd Design Automation Conference Proceedings, pp 715 - 719, 1985 .
9.
R.E. Bryant , D. Beatty, K. Brace, K. Cho, and T. Sheffler, "COSMOS: A Compiled Simulator for MOS circuits," ACM IEEE 24th Design Automation Conference Proceedings, pp 9 - 16, 1987.
10.
Patrick A. Duba , Rabindra K. Roy, Jacob A. Abraham, and William A. Rogers, "Fault Simulation in a Distributed Environment," ACM IEEE 24th Design Automation Conference Proceedings, pp 686 - 691, 1988 .
11.
H. Fujiwara , Logic Testing and Design for Testability, MIT Press, pp 84-102, 1985.
Masato Kawai and John P. Hayes, "An Experimental MOS Fault Simulation Program CSASIM," IEEE 21st Design Automation Conference Proceedings, pp 2 - 9,1984.
14.
S.A. Kravitz, R.E. Bryant, and R.A. Rutenbar, "Massively Parallel Switch-level Simulation: A Feasibility Study," IEEE Transactions On Computer-Aided Design, vol. 10, no. 7, pp 871-894, 1991.
15.
T. Lee and I. Haji, "A Switch-Level Matrix Approach to Transistor-Level Fault Simulation ," Proc. ICCD, pp 554-557, Nov.1991.
16.
N. Manjikian and W. Loucks, "High Performance Distributed Logic Simulation On A Network of Workstations," 7th Workshop on Distributed and Distributed Simulation, pp 76 - 84, July 1993 .
17.
W. Meyer and Raul Camposano, "Fast Hierarchical Multi-Level Fault Simulation of Sequential Circuits with Switch-Level Accuracy," ACM IEEE 30th Design Automation Conference Proceedings, pp 515 - 519,1993.
18.
R.B. Mueller-Thuns , D.G. Saab, and J.A. Abraham, "Distributed VLSI Switch-level Simulation ," ICCAD proceedings , 1990.
19.
R.B. Mueller-Thuns, D.G. Saab, R.F. Damiano and J.A. Abraham, "VLSI Logic and Fault Simulation on General-Purpose Distributed Computers," IEEE Trans. CAD., vol 12, no. 3, pp 446 - 460, March 1993.
20.
S. Patil and P. Banerjee, "Performance Trade-Offs in a Distributed Test Generation/Fault Simulation Environment," IEEE Trans. CAD., vol 10, no 12, pp 1542 -1558, Dec.1991.
21.
C.A. Ryan and J.G. Tront, "On Parallel Switch-level Fault Simulation," 11th IEEE VLSI Test Symposium, Atlantic City, New Jersey pp 341 - 347, April 1993.
22.
C.A. Ryan, "Parallel Hardware Accelerated Switch-level Fault Simulation," Ph.D. Dissertation, Virginia Polytechnic Institute and State University , Blacksburg, VA, 1993.
23.
John P. Shen, W. Maly, and F. Joel Ferguson, "Inductive Fault Analysis of MOS Integrated Circuits," IEEE Design and Test of Computers, vol 5, no 4, pp 13-26, Dec. 1985 .
24.
Hsi-Ching Shih, Joseph T. Rahmeh, and Jacob A. Abraham, "FAUST: An MOS Fault Simulator with Timing Information," IEEE Transactions on Computer-Aided Design, vol 5, no 4, pp 557-563, Oct.1986.
25.
Mark T. Smith , "A Hardware Switch Level Simulator for Large MOS Circuits," ACM IEEE 24th Design Automation Conference Proceedings, pp 95 - 100, 1987.
26.
C. Sporrer and H. Bauer, "Corolla Partitioning for Distributed Logic Simulation of VLSI-Circuits ," 7th Workshop on Distributed Simulation, pp 85 - 92, July 1993.
27.
Synopsys-The Synthesis Company, VHDL System Simulator Reference Manual, 1994.
