This paper presents programs and models for interfacing VLSI design tools and the VHDL hardware description language. The programs convert CIF files to VHDL component instantiation lists, and extract timing parameters from Spice transistor specifications. The models are simulatable VHDL descriptions for the instantiated components. We will describe various linking alternatives and the details of a switch level linkage. This technique will be useful in an academic setting for integrating VHDL into Magic tool-set.
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References
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Navabi, Z., VHDL: Analysis and Modeling of Digital Systems, McGraw-Hill Publishing, New York, NY, 1993.
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J. Dube and Z. Navabi, "Behavioral VHDL transistor slope models", Proceedings of the 1991 IEEE ASIC Conference and Exhibit, Sept. 1991.
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Navabi, Z., and Z. Razavi, "Self Adjusting Unidirectional Switch Models for Dynamic Load Calculation and Fast Switch Level Simulation", Proceedings of the Spring '93 Conference of the VHDL International Users Forum, Ottawa, Canada, April 1993.
