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Abstract

Accurate circuit modeling and simulation of Silicon-on-Insulator (SOI) enhancement and depletion Junction Field-Effect transis tors (JFETs) is presented. The nonuniformity in FET device parameters along the channel depth (due to fabrication processes), is taken into account. This is typical in SOI and other thin-film struc tures. Since SOI fabrication processes parameters are represented, in our model, by a closed form mobility variation, improved model accuracy is guaranteed. Simulation results are found to be within less than 3% of actual measurements. Small-signal circuit-model parameters are determined for SOI FJETs and then evaluated for further logic applications. Inverters with a channel Enhancenient-JFET (E-JFET) drivers and n- channel depletion-JFET loads (E/D invert ers) are also considered with different supply voltage values, device parameters and digital applications.

Keywords

Process-dependent circuit modeling and simulation thin film silicon-on insulator junction field effect transistors VLSI logic circuits enhancement- JFETs.

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Process-Dependent Circuit Modeling and Simulation of SOI JFETs: Digital VLSI Applications

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