We describe a nonlinear computer simulation model of an Ana log Charge-Pump Phase Locked Loop (ACP-PLL). Offsets of the Phase Detector and Analog Charge-Pump are modeled as dis turbances to simulate their effects on the steady-state phase error of the loop.
An extensive computer simulation study is carried out for the design of an example Analog CP-PLL using the proposed non linear model and comparing it to the conventional linear model. Results demonstrate the linear model is not sufficient to fully analyze and predict the behaviour of the Analog CP-PLL.
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