Design and Simulation of a New Queuing Architecture for Large-Scale ATM Switches

Abstract

The authors study the different buffering techniques used in the literature to solve the contention problem in asynchronous transfer mode (ATM) switching architectures. The objective of this study is to determine the buffer requirements needed to achieve a given quality of service (e.g., a given cell loss probability). On the basis of this study, the authors propose a combined central and output queuing (CCOQ) technique to be used in designing large-scale ATM switches. Also, a general design technique for an N×N large-scale ATM switch is proposed with a suitable CCOQ buffer size to reduce both the cell loss probability and the complexity of the memory modules. The switch has to be designed such that it can be implemented using the smallest number of VLSI chips possible. It should be also reliable for commercial use. The switch should support multicast and priority control functions.