The feasibility of employing a microprocessor to perform the various tasks involved with the implementation of a number of well known error-control coding schemes is investigated. It is demonstrated that reasonable data-rates can be achieved with even quite powerful codes.
Get full access to this article
View all access options for this article.
References
1.
PetersonW. W., Error Correcting Codes, MIT Press, (1961).
2.
BerlekampE. R., Algebraic Coding Theory, McGraw-Hill, (1968).
3.
DavidaG. I., ‘Decoding of BCH codes’, Electronics Letters, 7, p. 664, (November, 1972).
4.
ChienR. T., ‘Cyclic decoding procedures for Bose-Chaudhuri-Hocquenghem codes’, IEEE Trans Inf. Th., IT-10, pp. 357–363, (October, 1964).
5.
MasseyJ. L., ‘Shift-register synthesis and BCH decoding’, IEEE Trans. Inf. Th., IT-15, pp. 122–127, (January, 1969).
6.
DavidaG. I., and CowlesJ. W., ‘Decoding of triple-error-correcting BCH codes’, Electronics Letters, 8.
7.
HartleyM. G., (ed), Digital Simulation Methods, chapter 3, Peter Perigrinus Ltd., (1975).
8.
AmblerA. P., ‘Applications of microprocessors to error control systems’, M.Sc. Thesis, University of Manchester, (1977).
