GhoshSRoyK.Parameter variation tolerance and error resiliency: new design paradigm for the nanoscale era. Proc IEEE2010;
98: 1718–1751.
2.
ChattopadhyaySTripathiSBGoswamiM, et al. Design of fault tolerant majority voter for TMR circuit in QCA. In: 2016 20th International Symposium on VLSI Design and Test (VDAT), 2016, pp.1–2. Guwahati, India: IEEE.
3.
AnjankarSCKolteMTPundA, et al.
FPGA based multiple fault tolerant and recoverable technique using triple modular redundancy (FRTMR). Procedia Comput Sci2016;
79: 827–834.
4.
ChenYKFengZGZhangSY, et al.
Research on reconfigurable triple-module redundancy space on-board computer. Comput Meas Control2017;
25: 201–203 (in Chinese).
5.
SioziosKSavidisISoudrisD. A framework for exploring alternative fault-tolerant schemes targeting 3-D reconfigurable architectures. In: International conference on embedded computer systems: architectures, modeling and simulation,2016, pp.336–341. Samos Island, Greece: IEEE.
6.
BanerjeeSRaoW. A local reconfiguration based scalable fault tolerant many-processor array. In: 22nd Asia and South Pacific design automation conference (ASP-DAC),2017, pp.432–437. Chiba, Japan: IEEE.
7.
HanJLeungELiuLB, et al. A fault-tolerant technique using quadded logic and quadded transistors. IEEE Transactions on very large scale integration systems, Vol.
23, 2015, pp.1562–1566.
8.
PierceWH.Interwoven redundant logic. J Franklin Inst1964;
277: 55–85.
9.
ZhangJBCaiJYMengYF.A design technology of fault tolerance circuit system facing complex electromagnetic environments. J XI’AN Jiaotong Univ2017;
51: 53–59 (in Chinese).
10.
SolovievAStempkovskyA. Methods of increasing the fault-tolerance of control unit by introducing hardware redundancy. In: Internet technologies and applications. Wrexham, UK: IEEE, 2015, pp.37–40.
11.
Von NeumannJ.Probabilistic logics and the synthesis of reliable organisms from unreliable components. In: ShannonCEMccarthyJ (eds) Automata studies.
Princeton:
Princeton University Press, 1956, pp.43–98.
12.
DobrushinROrtyukovE.Upper bound on the redundancy of self-correcting arrangements of unreliable functional elements. Prob Inf Trans1977;
13: 82–89.
13.
PippengerNStamoulisGDTsitsiklisJN.On a lower bound for the redundancy of reliable networks with noisy gates. IEEE Trans Inform Theory1991;
37: 639–643.
14.
HanJJonkerP.A system architecture solution for unreliable nanoelectronic devices. IEEE Trans Nanotechnol2002;
1: 201–208.
15.
HanJJonkerP.A defect- and fault-tolerant architecture for nanocomputers. Nanotechnology2003;
14: 224–230.
16.
BeiuVIbrahimW.Devices and input vectors are shaping von Neumann multiplexing. IEEE Trans Nanotechnol2011;
10: 606–616.
17.
RoySBeiuV.Majority multiplexing- economical redundant fault-tolerant designs for nanoarchitectures. IEEE Trans Nanotechnol2005;
4: 441–451.
18.
IbrahimWBeiuVBegA. On NOR-2 von Neumann multiplexing. In: 2010 5th international design and test workshop, Abu Dhabi, United Arab Emirates: IEEE, 2010, pp.67–72.
19.
QiYGaoJBFortesAB.Markov chains and probabilistic computation – a general framework for multiplexed nanoelectronic systems. IEEE Trans Nanotechnol2005;
4: 194–205.
20.
VoicuGRCotofanaSD. Towards heterogenous 3D-stacked reliable computing with von Neumann multiplexing. In: 2013 IEEE/ACM international symposium on nanoscale architectures, 2013, pp.122–127.
21.
GucwaK. On simulation of multiplexed architecture for fault-tolerant nanoelectronic systems. In: 12th IEEE conference on nanotechnology, Vol.
7, 2012, pp. 1–4.
GubskyDZemlyakovV.Advanced microwave equipment simulator for engineering education. Int J Electr Eng Educ2019;
56: 92–101.
24.
ZineOErrouhaMZamzoumO, et al.
SEITI RMLab: a costless and effective remote measurement laboratory in electrical engineering. Int J Electr Eng Educ2019;
56: 3–23.
25.
DiaoMYuLHChenXB.On redundancy-modified NAND multiplexing. J Syst Eng Electron2018;
4: 864–872.
