Adopting a low hardware redesigned architectural design for educational environment by using DFE-based 5G communication

Abstract

In this paper, we adopt a proposal to reduce the complexity and increase the throughput in time domain using 5G. This is achieved by speeding up the conventional architecture in advance. Using this method, the number of coefficients of feedback filter is reduced, thus decreasing the hardware complexity. The convergence strategy and steady state error performance are also increased without any additional hardware requirements. This is based on storing the past values of decision maker in a separate look up table and updating it time to time using parallel error multiplexer. Using this method, the results are very efficient by decreasing the power, area and logic utilization of the new architecture. If we include this concept as a hands-on experience, students can learn and also optimize the architecture easily.

Keywords

Decision feedback equalizer 5G parallel error multiplexer inter-symbol

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