An enhanced model predictive control method with reduced computational load for three-level T-type inverter

Abstract

Among three-level inverter topologies, the T-type configuration has gained prominence in low-voltage applications due to its favorable performance characteristics. Model predictive control has attracted considerable interest for such converters, offering the advantages of various control targets and a rapid dynamic response. However, the conventional approach is burdened by high computational load. In this study, the proposed strategy provides fewer evaluation times by reducing the number of rolling optimization by grouping candidate vectors. A novel sector-based distribution of candidate voltage vectors determined by the reference vector’s angular location is presented. By restricting the control cycle to the assessment of only seven candidate voltage vectors, the computational load is substantially reduced. Furthermore, the strategy effectively mitigates common-mode voltage, enhances current waveform quality, and decreases power dissipation in the switching devices without relying on a weighting factor. The proposed approach’s validity and effectiveness are demonstrated through simulation and experimental results applied to T-type inverter.

Introduction

For renewable and sustainable energy systems, the requirements for maintaining high power quality and achieving superior energy efficiency have become increasingly significant in low-voltage (LV) applications. Therefore, both inverter topologies and control strategies play a fundamental role in enhancing energy conversion efficiency and ensuring high-quality power delivery.

The two-level inverter offers ease of control due to its simple and cost-effective structure. However, its main drawbacks include high switching losses, high harmonic distortion, and the requirement for large filters. In medium-voltage applications, three-level inverters are frequently employed due to their performance advantages. The most widely implemented inverter structures include the diode- and active-neutral-point-clamped (NPC) types, along with cascaded H-bridge and flying capacitor configurations.^1–3 Three-level inverter topologies provide a superior harmonic profile, low-voltage stress, and switching losses. Despite their advantages, these topologies are not well-suited for low-power and LV applications because of the control complexity introduced by the higher number of semiconductor devices. ⁴ To overcome the existing limitations, the three-level T-type inverter (3LT²I) has been developed, which effectively merges the benefits of two-level inverters such as including simple operation principle, fewer component requirements, and low conduction losses, with the superior harmonic performance and reduced switching losses characteristic of three-level inverters. ⁵ Despite the mentioned benefits of the 3LT²I, its control strategy is inherently more complex than that of a conventional two-level inverter. In addition, 3LT²I suffers from voltage imbalance across the DC-link capacitors similar to NPC inverters, as well as common-mode voltage (CMV) phenomena inherent to characteristics of inverters. ⁶

CMV resulting from fast-switching and dead-time effect contribute significantly to electromagnetic interference (EMI) in inverter systems. ⁷ CMV fluctuations cause voltage stress in windings and bearing leakage currents in electrical machines. ⁸ Moreover, CMV generates leakage current in grid-tied PV systems without transformers, where the amplitude of these currents directly depends on CMV fluctuations. ⁹ Therefore, one of the approaches to eliminating or minimizing CMV is preferred. The CMV mitigation approach is more suitable for multi-objective constraints in model predictive control (MPC). ¹⁰ Besides, the neutral-point voltage (NPV) oscillation can increase voltage stress on capacitors and switching devices, compromising system reliability and leading to output current distortion. ¹¹

Conventional control strategies for grid-tied three-level inverters comprise linear control, hysteresis control, and advanced versions of these controls.^12–14 With the advancement of microcontroller technologies, MPC has gained recognition as a viable technique for managing power converters. Its key advantages include the ability to handle multiple control targets and system constraints within the same control loop, enhanced dynamic performance, and simplified design. ¹⁵ The basic steps in MPC include predicting the future control behavior for the next sampling instant based on a discrete-time model, evaluating deviations between reference and predicted values expressed through a cost function, and applying the optimal switching action that minimizes the cost function. Moreover, MPC is particularly advantageous for dealing with the inherent nonlinearities and discrete switching behavior of power converters, thereby eliminating the need for traditional elements, such as the PI controller and modulation stage. ¹⁶

Various strategies have been proposed for MPC to mitigate NPV oscillations and suppress CMV fluctuations, such as optimizing voltage vector (VV) selection to minimize CMV in a 3LT²I, ¹⁷ employing a predefined vector table to achieve NP potential balance, ¹⁸ and adding the control objective of capacitor voltage balancing in the global cost function. ¹⁹ Nonetheless, these strategies cause deterioration in the current quality. Several MPC approaches employing virtual VVs that do not affect NPV have been proposed in.^20,21 However, these strategies significantly increase the switching frequency.

In conventional MPC, increasing numbers of VVs contribute more to the computational load in three-phase three-level inverters. Therefore, it is important to achieve multi-objective control inherently with the candidate VVs without adding any control objective to the cost function to prevent an increase in the computational load. Xia et al. ²² proposed a single-prediction MPC that evaluates 12 candidate VVs for each of the 6 sectors of the space vector diagram. However, incorporating CMV into the cost function combined with the NPV constraint inevitably increases execution time. Hu et al. ²³ developed a double-step MPC with six sectors and six VVs per sector. Nevertheless, CMV mitigation was omitted, while NPV balancing was incorporated into the cost function, and the reported THD remained relatively high. Yang et al. ²⁴ classified VVs into two groups based on DC-link capacitor voltage comparisons to maintain NPV balance. Nevertheless, evaluating 21 VVs in each iteration imposes a significant computational load, while the resulting control strategy suffers from large CMV fluctuations. Wang et al. ²⁵ designed a model predictive power control strategy with 7 candidate VVs per sector by dividing the space vector diagram into 12 sectors. However, the strategy produces large CMV fluctuations and relatively high THD. Overall, the aforementioned strategies lack the capability to inherently constrain the CMV, and the large number of dV/dt stresses caused by transitions between selected VVs may need to be constrained in the cost function.^22–25 Liu et al. ²⁶ introduced a double-vector MPC approach to reduce CMV by reclassifying candidate voltage vectors without using a weighting factor. Nevertheless, this approach results in a notably higher switching frequency compared with the classical approach. However, the power losses associated with switching transitions were not considered in the candidate VVs selection table of the aforementioned studies.

This paper presents an MPC strategy designed to mitigate CMV, decrease power losses in switching devices, and reduce computational load without relying on a weighting factor. The essential innovations and original contributions of this paper can be summarized as follows:

• The execution time is reduced by limiting and regrouping the number of candidate VVs per control cycle and employing a short prediction horizon to compensate for computational delay.

• Despite the narrowed selection of candidate VVs per control cycle, the proposed MPC strategy achieves superior output current quality. Moreover, the current quality is improved by lower switching frequency and reduced power dissipation in the switching devices.

• To restrict the CMV magnitude, the MPC strategy omits the VVs that generate large CMV fluctuations from the candidate set. Thus, CMV suppression is inherently achieved, eliminating the need for a weighting factor.

The remainder of this paper is organized as follows: Section II presents the mathematical model of the three-phase 3LT²I, including its operating principles and system equations. Section III outlines the proposed MPC scheme, including the formulation of a control strategy and reduction of the computational burden. To validate the proposed control approach, a comprehensive set of simulation and experimental studies is presented in Section IV. Finally, Section V provides a summary of the conclusions drawn from this study.

Operating principles of the 3LT²I

In each phase leg of the 3LT²I, the upper $(S_1)$ and lower $(S_4)$ switches constitute a half-bridge module that blocks the entire bus voltage, whereas the bidirectional switch at the midpoint $(S_2$ and $S_3$ ) operate as a neutral-point clamping module that blocks half of the bus voltage, as illustrated in Figure 1 with the inverter power circuit connected to the grid through an L filter. This arrangement leads to lower switching and conduction losses compared to conventional half-bridge structures.

Figure 1.

Circuit topology of three-phase 3LT²I.

Switches $S_1$ and $S_2$ turn-on for any phase are defined as the output voltage (P) and the output voltage $V_{\mathrm{xO}}$ {x = a, b, c} is $+V_{\mathrm{DC}}/2$ . When $S_2$ and $S_3$ switches turn on, the neutral voltage level (O) is obtained and $V_{\mathrm{xO}}$ is 0. Finally, when $S_3$ and $S_4$ turn-on, a negative output voltage (N) of $-V_{\mathrm{DC}}/2$ is generated. Under the assumption that the DC-link capacitor voltages are balanced $(V_{C1}=V_{C2})$ , the correspondence between switching states and output voltage for phase legs is given as follows:

$$v_{\mathrm{xO}}=S_x(V_{\mathrm{DC}}/2)$$

(1)

As depicted in Figure 2, the three-phase 3LT²I generates a total of 27 voltage space vectors, 19 non-redundant and 8 redundant, with P, O and N switching state combinations in each phase leg. The VVs are divided into four categories as zero VVs $V_0$ , small VVs in pairs $V_{\mathrm{SPi}}$ and $V_{\mathrm{SNi}}$ , medium VVs $V_{\mathrm{Mi}}$ and large VVs $V_{\mathrm{Li}}$ according to their amplitudes, where $i=1,\dots ,6$ .

Figure 2.

Space VVs diagram of a three-phase 3LT²I.

Space VVs can affect the voltage values across bus capacitors $C_1$ and $C_2$ . This may cause an increase in the voltage stress on the capacitors, affecting the system reliability and causing harmonics in the output voltage. ¹¹

No variations in capacitor voltages occur with zero and large VVs, which prevents voltage imbalance at the neutral point. Medium VVs influence the NPV according to the direction of the neutral-point current. In small VVs, each vector has two different switching states called P and N type. P type vectors discharge the upper capacitor $C_1$ , decreasing the voltage $V_{C1}$ and increasing the voltage $V_{C2}$ . Conversely, N type vectors discharge the lower $C_2$ capacitor, decreasing the voltage $V_{C2}$ and increasing the voltage $V_{C1}$ . This analysis is for the T-type converter operating in inverter mode and vice versa in rectifier mode.

CMV denotes the potential difference occurring between the grid neutral node (n) and the DC bus midpoint (O). CMV of the three-phase 3LT²I is represented as the pole voltages relative to the DC bus neutral point, ²⁷ and it can be obtained as:

$$v_{\mathrm{cmv}}=v_{\mathrm{aO}}+v_{\mathrm{bO}}+v_{\mathrm{cO}}/3$$

(2)

The 3LT²I is capable of generating CMV levels of $\pm V_{\mathrm{DC}}/2$ , $\pm V_{\mathrm{DC}}/3$ , $\pm V_{\mathrm{DC}}/6$ , and 0. Based on these voltage levels, the 27 switching states can be categorized into seven distinct groups, each corresponding to a specific CMV magnitude, as detailed in Table 1.

Table 1.

Effect of switching states on CMV in 3LT²I.

Switching states	CMV	Group
PPP	$V_{\mathrm{DC}}/2$	G1
PPO, OPP, POP	$V_{\mathrm{DC}}/3$	G2
POO, OPO, OOP, PPN, NPP, PNP	$V_{\mathrm{DC}}/6$	G3
OOO, PON, OPN, NPO, NOP, ONP, PNO	0	G4
OON, NOO, ONO, PNN, NPN, NNP	$-V_{\mathrm{DC}}/6$	G5
ONN, NON, NNO	$-V_{\mathrm{DC}}/3$	G6
NNN	$-V_{\mathrm{DC}}/2$	G7

Using Kirchhoff’s Voltage Law, the dynamic equations of a 3LT²I connected to the network with an L filter are derived as follows:

$$v_{\mathrm{xn}}=R_f{i}_{\mathrm{gx}}+L_f({\mathrm{di}}_{\mathrm{gx}}/\mathrm{dt})+v_{\mathrm{gx}}$$

(3)

where ${\mathit{v}}_{\mathit{xn}}$ , ${\mathit{i}}_{\mathit{gx}}$ , and ${\mathit{v}}_{\mathit{gx}}$ represent the inverter output voltages with respect to the grid neutral, the grid currents, and the grid voltages, respectively, in abc-frame. ${\mathit{L}}_{\mathit{f}}$ denotes the filter inductance and ${\mathit{R}}_{\mathit{f}}$ refers to its internal resistance.

Proposed model predictive control scheme

The state-space model of the system transformed into the dq-axis rotating reference frame is formulated as:

$$\stackrel{·}{i}\left(t\right)=\mathbf{A}{i}_{g,\mathrm{dq}}\left(t\right)+{\mathbf{B}}_{\mathbf{i}}{v}_{i,\mathrm{dq}}\left(t\right)+{\mathbf{B}}_{\mathbf{g}}{v}_{g,\mathrm{dq}}\left(t\right)$$

(4)

where A, ${\mathbf{B}}_{\mathbf{i}}$ , and ${\mathbf{B}}_{\mathbf{g}}$ matrices are as:

$$\mathbf{A}=\left[\begin{array}{cc}-\frac{R_f}{L_f}\hfill & {\omega }_g\hfill \\ \multicolumn{1}{c}{-{\omega }_g}& -\frac{R_f}{L_f}\hfill \end{array}\right],{\mathbf{B}}_{\mathbf{i}}=\left[\begin{array}{cc}\frac{1}{L_f}\hfill & 0\hfill \\ \multicolumn{1}{c}{0}& \frac{1}{L_f}\hfill \end{array}\right],{\mathbf{B}}_{\mathbf{g}}=\left[\begin{array}{cc}-\frac{1}{L_f}\hfill & 0\hfill \\ \multicolumn{1}{c}{0}& -\frac{1}{L_f}\hfill \end{array}\right]$$

(5)

where ${\omega }_g$ is the grid angular frequency.

The dynamic system model is discretized using the forward Euler approximation due to its simplicity and its suitability for systems that are both cross-coupled and linear time-invariant.

$$\left[\begin{array}{c}{i}_{\mathrm{gd}}(k+1)\hfill \\ \multicolumn{1}{c}{i_{\mathrm{gq}}(k+1)}\end{array}\right]=\mathbf{F}\left[\begin{array}{c}{i}_{\mathrm{gd}}(k)\hfill \\ \multicolumn{1}{c}{i_{\mathrm{gq}}(k)}\end{array}\right]+{\mathbf{G}}_{\mathbf{i}}\left[\begin{array}{c}{v}_{\mathrm{id}}(k)\hfill \\ \multicolumn{1}{c}{v_{\mathrm{iq}}(k)}\end{array}\right]+{\mathbf{G}}_{\mathbf{g}}\left[\begin{array}{c}{v}_{\mathrm{gd}}(k)\hfill \\ \multicolumn{1}{c}{v_{\mathrm{gq}}(k)}\end{array}\right]$$

(6)

where the value of the variable in the dq-axis $k\in \mathbb{N}=\{0,1,2,\dots \}$ indicates the steps at the discrete time instant. The discrete-time state-space matrices $\mathbf{F}$ , ${\mathbf{G}}_{\mathbf{i}}$ , and ${\mathbf{G}}_{\mathbf{g}}$ can be expressed as:

$$\{\begin{array}{c}\multicolumn{1}{c}{\mathbf{F}\approx \mathbf{I}+\mathbf{A}{T}_s}\\ \multicolumn{1}{c}{{\mathbf{G}}_{\mathbf{i}}\approx {\mathbf{B}}_{\mathbf{i}}{T}_s}\\ \multicolumn{1}{c}{{\mathbf{G}}_{\mathbf{g}}\approx {\mathbf{B}}_{\mathbf{g}}{T}_s}\end{array}$$

(7)

where $\mathbf{I}$ is the two-dimensional identity matrix and $T_s$ is the sampling time.

The computational load of the system rises owing to the numerous switching state combinations and feedback components involved in the inverters. The computation time causes a time delay in the real-time control system. To compensate for the delay, the corresponding switching state is applied in the following sampling period. The one-sample ahead prediction with delay compensation was used to estimate the control variable at time $(k+1)$ with the optimal VV $(v^{\mathrm{op}})$ was applied at time $(k)$ . The estimated $\hat{i}(k+1)$ with combinations of switching states are used to predict the value of the variable at time $(k+2)$ . At instant $(k+1)$ , the optimal VV is implemented, determined by the switching state that minimizes the error at instant $(k+2)$ . The generic form of the system model shifted one step forward is expressed as:

$$\begin{array}{c}\multicolumn{1}{c}{\hat{i}(k+1)=\mathbf{F}i\left(k\right)+\mathbf{G}{v}^{\mathrm{op}}\left(k\right)}\end{array}$$

(8)

$$\begin{array}{c}\multicolumn{1}{c}{\begin{array}{c}\multicolumn{1}{c}{i^p(k+2)=\mathbf{F}\hat{i}(k+1)+\mathbf{G}{v}^p(k+1)}\end{array}}\end{array}$$

(9)

where superscript $p$ indicates the predicted variables.

The error between the predicted actuation output for the control objectives and constraints and the behavior of the system is evaluated in a cost function in the MPC. The objective of the cost function is to determine the switching state combination that produces the minimum cost value and then apply the switching state to the inverter directly. Here, the global cost function $g_{\mathrm{op}}$ with current control as the primary control objective can be formulated as follows:

$$g_{\mathrm{op}}=|{i_{\mathrm{dq}}}^{*}\left(k\right)-{i_{\mathrm{dq}}}^p(k+2)|$$

(10)

The switching transitions of the inverter bridge leg output from the positive (P) state to the negative (N) state and vice versa are eliminated within the control algorithm. This approach has been implemented across all control strategies to ensure a fair comparison.

The classic MPC evaluates 27 iterations for 3LT²I with 27 switching state combinations in each cycle to determine the optimal VV in each control step. However, considering all switching states for optimization significantly increases the computational burden. Figure 2 illustrates the division of the space vector diagram into six sectors. The position of the VV is determined by the phase angle $({\theta }_g)$ , which is obtained from the phase-locked loop (PLL). Thus, the location of reference vector allows for the selection and application of relevant candidate vectors in control algorithm. The candidate VVs can be grouped according to sectors, as shown in Table 2.

Table 2.

Sector-based classification of candidate VVs.

Sector	Candidate VVs
	Zero	Small	Medium	Large
I	$V_{0O}$	$V_{\mathrm{SP}1},V_{\mathrm{SN}2}$	$V_{M6},V_{M1}$	$V_{L1},V_{L2}$
II	$V_{0O}$	$V_{\mathrm{SN}2},V_{\mathrm{SP}3}$	$V_{M1},V_{M2}$	$V_{L2},V_{L3}$
III	$V_{0O}$	$V_{\mathrm{SP}3},V_{\mathrm{SN}4}$	$V_{M2},V_{M3}$	$V_{L3},V_{L4}$
IV	$V_{0O}$	$V_{\mathrm{SP}3},V_{\mathrm{SN}4}$	$V_{M3},V_{M4}$	$V_{L4},V_{L5}$
V	$V_{0O}$	$V_{\mathrm{SP}5},V_{\mathrm{SN}6}$	$V_{M4},V_{M5}$	$V_{L5},V_{L6}$
VI	$V_{0O}$	$V_{\mathrm{SN}6},V_{\mathrm{SP}1}$	$V_{M5},V_{M6}$	$V_{L6},V_{L1}$

The proposed strategy reduces the number of iterations in each control loop by using seven candidate VVs per sector. Thus, excluding non-relevant candidate vectors from the reference vector in the cost function evaluation reduced the computational load of the proposed strategy. Furthermore, by eliminating the VVs that generate large CMV and using only the G3, G4, and G5 vectors, the proposed strategy reduces the magnitude of the CMV without requiring a weighting factor.

The proposed MPC algorithm is illustrated in Figure 3, with the control process executed as follows:

• (1) Measuring phase/load currents, phase/load voltages and DC bus voltages at $(k)$ sampling instants and converting from three phase signals to dq frame.

• (2) Estimating the dq frame currents at sampling time $(k+1)$ with the optimum switching signal $S_{\mathrm{xj}}^{\mathrm{op}}$ applied at the previous sampling interval. The estimated currents are generated by (8).

• (3) Determining candidate VVs by sector using the phase/load angle $({\theta }_g)$ .

• (4) Predicting of dq frame currents at instant $(k+2)$ using (9).

Figure 3.

Overview of the proposed MPC structure.

Evaluating the cost function (10) for each of the candidate VVs reduced from 27 to 7 with the proposed strategy and applying the minimum cost value producing switching state to the inverter. Storing the optimum switching state for the next loop.

Simulation and experimental results

In this paper, the proposed MPC method is compared with strategies^22–26 in literature to verify its applicability and superiority. To make a fair performance comparison, the candidate VV selection table of the compared methods are evaluated using the same control strategy as candidate VV selection table of the proposed method. Here ²⁵ is not suitable for reference tracking when the load current is greater than 5 A because it generates reactive power in the unity power factor reference conditions. Therefore, it has been excluded from certain comparisons for reference values greater than 5 A.

Simulation results

The effectiveness of the proposed MPC strategy is demonstrated by detailed simulation studies in the MATLAB/Simulink environment. Table 3 summarizes the parameters of the 3LT²I and the overall system. The current harmonics, power tracking and response, CMV, NPV, device power losses, and switching frequency performances of the strategies are examined in Figures 4 to 11.

Table 3.

Parameters of the system.

Description	Symbol	Value
DC bus voltage	$V_{\mathrm{DC}}$	380 V
DC-link capacitor	$C_1,C_2$	470 μF
Line voltage (rms)	$v_{g,\mathrm{ll}}$	220 V
Nominal frequency	$f$	50 Hz
Filter inductance	$L_f$	15 mH
Filter resistance	$R_f$	0,2 Ω
Sample time	$T_s$	50 μs

Figure 4.

Comparison of load current THD performances of the strategies.

Figure 5.

Active power tracking error comparison among the strategies.

Figure 6.

Reactive power tracking error comparison among the strategies.

Figure 7.

Transient-state response of active power to a step change.

Figure 8.

Waveforms of CMV for the strategies: (a) ²² , (b) ²³ , (c) ²⁴ , (d) ²⁵ , (e) ²⁶ , and (f) proposed strategy.

Figure 9.

Comparison of NPV performances of the strategies.

Figure 10.

Comparative analysis of power loss distribution for the proposed and alternative strategies: (a) ²² , (b) ²³ , (c) ²⁴ , (d) ²⁵ , (e) ²⁶ , and (f) proposed strategy.

Figure 11.

Average switching frequency comparison relative to the reference current.

The total harmonic distortion (THD) of the load current of the strategies is shown in Figure 4 for reference current ranging from 1 to 8 A. The proposed, ²² and ²⁴ strategies keep below the THD limit specified in IEEE 519-2022 standard ²⁸ when the load current is greater than 2 A. Moreover, the proposed and ²⁴ strategies cause the lowest THD in the range from 5 to 8 A. As the load current increases, THD is reduced from 10.34% to 1.29%, from 9.51% to 2.00% and from 9.60% to 1.17% for the proposed, ²² and ²⁴ strategies, respectively.

The tracking errors in active and reactive power for the considered strategies are calculated and compared. The mean absolute percentage errors, defined relative to the apparent power $S$ , can be represented as:

$$\%e_P=(\left(\frac{1}{n}\sum _{k=0}^n|P^{*}\left(k\right)-P\left(k\right)|\right)/S)\times 100$$

(11)

$$\%e_Q=(\left(\frac{1}{n}\sum _{k=0}^n|Q^{*}\left(k\right)-Q\left(k\right)|\right)/S)\times 100$$

(12)

$n$ represents the number of samples. $P^{*}$ , $Q^{*}$ and $P$ , $Q$ correspond to the reference and measured active and reactive power, respectively.

The active and reactive power errors exhibit almost decreasing trends as the load current increases as presented in Figures 5 and 6, respectively. The proposed strategy has a lower rank than the strategies ²² and ²⁴ for active power tracking error ranking to reference current is 4 A, whereas above 4 A it produces the lowest active error rate. For instance, while the active power error of the proposed strategy at 8 A is 0.7%, the active power errors of the strategies ranked in citation order are 0.77%, 0.86%, 0.71%, 1.5% and 1%, respectively. Similar observation can be made for the reactive power tracking error ranking. The reactive power error in the proposed strategy, ²² and ²⁴ decreases steadily as the reference current increases. The proposed strategy and ²⁴ exhibit similar performance at higher than 4 A. Besides, the proposed strategy has the lowest error rate in the range from 4 to 6 A. For instance, the reactive power tracking error for the proposed strategy is 5.98% at 1 A. Likewise, the reactive power tracking errors for the strategies ranked in citation order are 5.84%, 8.56%, 6.24%, 9.21% and 8.54%, respectively. Additionally, the dynamic response time of the proposed and the other strategies are nearly 3 ms to reference active power step change from 500 to 3000 W, as detailed in Figure 7.

Figure 8 shows the interval between 4 and 4.2 s as an example, as the CMV magnitude remains unchanged despite changes in current in all strategies. The CMV generated by the proposed and ²⁶ strategies are limited to $\pm V_{\mathrm{DC}}/6$  V, whereas in the other strategies it oscillates with a magnitude of $\pm V_{\mathrm{DC}}/3$  V. The proposed and ²⁶ strategies have better CMV reduction capacity than other strategies.

The mean absolute percentage error of the NPV deviation $(\%e_{\mathrm{vc}})$ for a three-level inverter is given by:

$$\%e_{\mathrm{vc}}=(\left(\frac{1}{n}\sum _{k=0}^n|V_{C1}(k)-V_{C2}(k)|\right)/V_{\mathrm{DC}})\times 100$$

(13)

The proposed strategy involves a trade-off between NPV balancing and other system performance constraints and control objectives. In other words, it has limited ability to mitigate NPV fluctuations compared to other strategies due to its candidate vector table. NPV fluctuation is limited from 0.77% to 2.54% when the current is increased from 1 to 8 A, as shown in Figure 9. However, the NPV fluctuation is effectively suppressed to an acceptable level in the proposed strategy.

Energy dissipation in a T-type inverter employing SiC MOSFET devices mainly composed of conduction and switching losses.

The conduction losses of a MOSFET can be written as ²⁹ :

$$P_{\mathrm{con}}=R_{\mathrm{DS}(\mathrm{on})}{I}_{\mathrm{Drms}}^2$$

(14)

where $R_{\mathrm{DS}(\mathrm{on})}$ is the equivalent drain-source open-state resistance and $I_{\mathrm{Drms}}$ is the open-state rms power device current.

The switching losses in MOSFETs occur during the transition between on-state and off-state. Hence, the switching energies ( $E_{\mathrm{sw}(\mathrm{on})}$ + $E_{\mathrm{sw}(\mathrm{off})}$ ) of a MOSFET can be approximated as follows:

$$E_{\mathrm{sw}(\mathrm{on})}=u_{\mathrm{DS}}{I}_D\frac{t_r{t}_{\mathrm{pl}(\mathrm{on})}}{2}+Q_{\mathrm{rr}}{u}_{\mathrm{DS}}$$

(15)

$$E_{\mathrm{sw}(\mathrm{off})}=u_{\mathrm{DS}}{I}_D\frac{t_f{t}_{\mathrm{pl}(\mathrm{off})}}{2}$$

(16)

where $u_{\mathrm{DS}}$ and $I_D$ represent the measured MOSFET drain-source voltage and drain current, respectively. The following parameters are approximated based on the design criteria using data from the datasheet of the power devices. $t_r$ denotes the rise time of the drain current after the gate voltage reaches the threshold value, whereas $t_f$ represents the fall time when the gate voltage decreases below the threshold. $t_{\mathrm{pl}(\mathrm{on})}$ refers to the time required to charge the gate-drain capacitance, whereas $t_{\mathrm{pl}(\mathrm{off})}$ represents the discharge time. $Q_{\mathrm{rr}}$ is the reverse recovery charge of the body diode, which contributes to reverse recovery losses. Thus, the switching losses of the MOSFET are determined by multiplying the total switching energy by the average switching frequency $f_{\mathrm{sw}}$ . The total switching losses are determined by summing the losses that occur during MOSFET turn-on and turn-off events.

$$P_{\mathrm{sw}}=(E_{\mathrm{sw},\mathrm{on}}+E_{\mathrm{sw},\mathrm{off}})f_{\mathrm{sw}}=P_{\mathrm{sw},\mathrm{on}}+P_{\mathrm{sw},\mathrm{off}}$$

(17)

Figure 10 illustrates the conduction and switching losses for all strategies with respect to the reference current. The analysis indicates that conduction losses escalate with increasing reference current values. Also, switching losses dominate the total loss under all operation conditions. The proposed strategy generated lower losses for both the conduction and switching losses at all reference currents. For instance, at a reference current of 1 A, the proposed strategy results in 31% lower switching losses compared to the strategy ²⁵ with the second-lowest loss generation. Moreover, the switching losses in the proposed strategy are 4.8% lower than those in the strategy ²³ with the second-lowest loss generation at 8 A.

Figure 11 shows the switching frequency comparisons between the mentioned candidate VV tables and the proposed method. In all strategies, the switching frequency tends to decrease almost with increasing load current. The analysis demonstrates that the proposed technique achieves reduced average switching frequencies relative to other control strategies under all reference current conditions.

Figure 12 shows the efficiency of the proposed strategy in comparison with existing strategies. Among the existing methods, the strategy in ²² achieves the lowest power loss of 9.86 W at a 1 A reference current. However, the proposed strategy further reduces this loss to 6.77 W. Consequently, the proposed strategy reaches an efficiency of 98.25%, providing a 0.80% enhancement over the 97.47% efficiency obtained in. ²² Furthermore, the proposed strategy maintains this high-efficiency performance consistently across a wide operating range, from 1 to 8 A.

Figure 12.

Efficiency comparison of the strategies.

In summary, the advanced features and potential limitations of the proposed MPC strategy are presented through a comparison with existing strategies in Table 4. Here, the proposed MPC strategy is shown to reduce computational time through a reorganized and grouped candidate VVs table, while maintaining output current quality with the lowest switching frequency and, therefore, the lowest power losses. Moreover, the CMV is inherently limited by the proposed strategy. In addition, studies^22–26 require a multi-objective cost function to reduce power losses, while studies^22–25 adopt similar formulations to suppress CMV fluctuations. However, the computational load of these strategies increases notably, leading to performance trade-offs with other control objectives, such as NPV balancing and current harmonic quality.

Table 4.

Comparison of MPC strategies in simulation.

Strategies	Proposed	Xia et al. 22	Hu et al. 23	Yang et al. 24	Wang et al. 25	Liu et al. 26
Inherent CMV suppression capability	Yes	No	No	No	No	Yes
Computation time	Low	Moderate	Low	High	Moderate	Low
Current harmonics	Low	Low	High	Low	High	Moderate
Current THD at 5 A	1.93%	2.03%	7.14%	1.89%	7.44%	2.94%
Average switching frequency at 5 A	1944 Hz	2189 Hz	2106 Hz	2176 Hz	2124 Hz	2340 Hz
Total losses at 5 A	11.61 W	14.31 W	13.65 W	14.09 W	13.70 W	15.76 W
NPV fluctuation (1–8 A)	Within ±20 V	Within ±10 V	Within ±20 V	Within ±10 V	Within ±25 V	Within ±15 V

Experimental results

An experimental system is built to verify the performance of the proposed MPC strategy. The laboratory test platform shown in Figure 13 includes a three phase 3LT²I prototype, gate drivers, galvanically isolated Hall effect current (LEM LTS 25-NP) and voltage (LEM LV 25-P) sensors for signals, and relay circuit for connection. The proposed control strategy was executed on a TMS320F28379D DSP within the Embedded Coder Support Package environment for Texas Instruments C2000 processors. THD values are obtained with Chauvin Arnoux CA 8336 power & quality analyzer.

Figure 13.

Visual overview of the experimental test platform.

The 3LT²I consists of Infineon IMW120R090M1H SiC MOSFET for half bridge switches and Infineon IMW65R072M1H SiC MOSFET for neutral point clamping switches. TI UCC5350SBD single channel isolated gate drive integrated circuit is used to drive the switches.

Experimental tests were conducted to evaluate the proposed MPC strategy with candidate VV tables, using an inverter connected to an L filter and a balanced three-phase resistive load, where the DC-link voltage and AC line voltage were set to 60 and 24 V, respectively, at frequency of 50 Hz. The proposed strategy’s execution time was compared to that of existing strategies. The fluctuations of CMV in both the proposed and existing strategies under steady-state operation were also assessed. Figures 14 and 15 display the results. Subsequently, experimental tests were conducted to demonstrate the steady-state performance of the proposed MPC strategy under linear loads of 100 Ω (Case 1) and 50 Ω (Case 2). To assess the dynamic performance of the proposed strategy under transient conditions, the linear load resistance was reduced step change from 100 to 50 Ω, or vice versa. The current tracking performance was validated by emulating the variable DC-link voltage typically present in renewable energy systems. Figures 16 to 24 depict the experimental results of the proposed MPC under various operating conditions.

Figure 14.

Comparison of the computational load for MPC strategies.

Figure 15.

Experimental waveforms of CMV for the strategies: (a) ²² , (b) ²³ , (c) ²⁴ , (d) ²⁵ , (e) ²⁶ , and (f) proposed strategy (5 V/div, 5 ms/div).

Figure 16.

Switching waveforms of the 3LT²I: (a) ${\mathit{S}}_{\mathit{1}}$ and ${\mathit{S}}_{\mathit{3}}$ and (b) ${\mathit{S}}_{\mathit{2}}$ and ${\mathit{S}}_{\mathit{4}}$ (20 V/div, 10 ms/div).

Figure 17.

Waveforms of line-to-line inverter output voltages: (a) Case 1 and (b) Case 2 (50 V/div, 10 ms/div).

Figure 18.

Waveforms of grid phase voltages: (a) Case 1 and (b) Case 2 (20 V/div, 10 ms/div).

Figure 19.

Waveforms of grid phase currents: (a) Case 1 and (b) Case 2.

Figure 20.

Harmonic spectrum of the phase currents: (a) Case 1 and (b) Case 2.

Figure 21.

Phasor diagram of phase voltages and currents: (a) Case 1 and (b) Case 2.

Figure 22.

Transient response of the phase current during a step change from Case 2 to Case 1.

Figure 23.

Upper and lower capacitor voltages and phase-A load current under step changes in reference currents.

Figure 24.

Waveform of phase-A load current under dynamic DC-link voltage.

Figure 14 presents the experimental results, showing the relative execution times of the compared methods and the proposed strategy as a percentage of the conventional MPC. The comparison of execution times was performed with Code Execution Profiling for Texas Instruments™ C2000, which shows the real-time execution profile. Moreover, the number of vectors evaluated per cycle by each control method is presented in Figure 14. The proposed strategy achieves a significant reduction in execution time, approximately 55.28%, relative to the conventional MPC. Moreover, the top three methods with the lowest computational load are^23,26 and the proposed strategy, respectively. Similarly, the proposed strategy is one of the three methods with the lowest number of iterations.

Figure 15 illustrates that the fluctuations of CMV for proposed MPC and existing strategies. The proposed MPC inherently limits the CMV generated by the 3LT²I, with a maximum magnitude of $\pm 10$  V, equivalent to $\pm 1/6$ of the DC bus voltage. However, when existing strategies (with the exception of ²⁶ ) are utilized, the CMV fluctuation magnitude reaches $\pm 20$  V, which is equivalent to $\pm 1/3$ of the DC bus voltage.

$S_3$ operates as the complement of $S_1$ and $S_2$ operates as the complement of $S_4$ with inserted dead-time to prevent short circuit in Figure 16. In the off-state, switches $S_1$ and $S_4$ block the entire DC bus voltage, while switches $S_2$ and $S_3$ block only half of the bus voltage. Figure 17 presents that the line-to-line voltage exhibits similar and good inverter output voltage characteristics in both test cases. The experimental waveform of the filtered grid phase voltage is shown in Figure 18(a) and (b) for Case 1 and Case 2, respectively. It can be observed that there is less ripple in the phase voltages. The THD of the phase voltages due to linear load is similar to the THD of the current.

Figure 19(a) and (b) show the waveforms of the phase currents for Case 1 and Case 2, respectively. The current THD is 4.2% and 3.1% for Case 1 and Case 2, respectively. As the reference current value increases, the current quality also increases in the proposed strategy. The harmonic spectrum shown in Figure 20(a) and (b) shows that the harmonic contents in both cases comply with the harmonic limits specified in the IEEE 519-2022 standard. The highest current distortion in Case 1 is 3.7%, whereas the highest current distortion in Case 2 is 2.9%, which is compatible with the fifth harmonic order with a harmonic limit of 4%. The voltage and current vector phasors are presented in Figure 21(a) and (b) for Case 1 and Case 2. Both cases demonstrate balanced phase angles between the current and voltage phasors.

The dynamic response of the current during a 100% step change in the three-phase linear load (from Case 2 to Case 1) is presented in Figure 22. The actual current converges to the reference in approximately 1.5 ms under real-time operation, whereas it takes around 1 ms in ideal simulation conditions due to the absence of hardware constraints. Figure 23 demonstrates that the capacitor voltage deviations are maintained within a ±6% band relative to the nominal capacitor voltages for a step change from Case 1 to Case 2. The proposed strategy ensures that the output current magnitude remains close to its reference value despite a 3.8 V peak-to-peak variation on the nominal 60 V DC-link voltage, as depicted in Figure 24. Therefore, the proposed strategy can be effectively applied to renewable energy systems characterized by variable DC-link voltages.

Conclusions

This paper proposes a reduced computational load MPC strategy for 3LT²I. In the proposed strategy, the control objective and system constraints are provided by a new candidate vector table without weighting factor. Moreover, the proposed strategy reduces both switching frequency and switching losses whereas preserving the current THD quality compared to similar works in the literature. The CMV amplitude is restricted to $\pm 1/6$ DC bus voltage without considering redundant vectors. Simulation and experimental results are compared for current THD, power tracking error, CMV, NPV, switching frequency and losses, and computational load to verify the applicability and validity of the proposed strategy. Evidently, the foremost advantage of the proposed strategy lies in its ability to seamlessly integrate simplicity with versatility. In the proposed strategy, balancing the DC capacitor voltages with the weighting factor can be added as a control target to reduce NPV fluctuations. Another approach is to increase the number of candidate vectors by one, which will cause a slight increase in the computational load. Future research will focus on further improvement of the proposed strategy and evaluating its performance across diverse platforms.