Sage Journals: Discover world-class research

Abstract

High temperature occurs in testing of complex System-on-Chip designs and it may become a critical concern to be carefully taken into account with continual development in Very Large Scale Integration technology. Peak temperature significantly affects the reliability and the performance of the chip. So it is essential to minimize the peak temperature of the chip. Heat generation by power consumption and heat dissipation to the surrounding blocks are the two prominent factors for the peak temperature. Power consumption can be minimized by a careful mapping of don’t cares in precomputed test set. However, it does not provide the solution to peak temperature minimization because the non-uniformity in spatial power distribution may create localized heating event called “hotspot.” The peak temperature on the hotspot is minimized by Genetic Algorithm–based don’t care filling technique that reduces the non-uniformity in spatial power distribution within the circuit under test while maintaining the overall power consumption at a lower level. Experimental results on ISCAS89 benchmark circuits demonstrate that 6%–28% peak temperature reduction can be achieved.

Keywords

Genetic algorithm power consumption heat generation circuit under test very-large-scale integration

Introduction

The rapid progression of semiconductor manufacturing technology has enabled the design and development of highly complex system-on-chip (SoC) designs. However, this evolution has posed challenges to the test community. The continued shrinking of the transistor size has increased the probability of manufacturing defects in the integrated circuits (ICs). When a system becomes more complicated, the testing process becomes more challenging. Power consumption during testing has been significantly higher compared to the normal operation mode due to substantially increased switching activity.^1,2 The power density of the ICs has been steadily growing simply because the number of transistors integrated into the silicon die has increased. The elevated levels of power density during test inherently increase overall circuit temperature and, at the same time, create localized heating events, called hotspots.^3,4 Peak temperature on hotspot significantly leads to a high cooling cost, a decrease in reliability or even permanent damage.

Early research efforts about low-power solutions fall into two categories: core-level design for testability (DFT) and system-level DFT.⁵ Consequently, traditional classes of low-power solutions targeting both methods have been proposed. Techniques falling in the former category include low-power scan architectures with gated clocks,^6,7 scan cell and test pattern reordering,^8,9 and low-transition test pattern generation algorithms.¹⁰ This category consists of reordering techniques that reduce the switching activity by modifying the test vector order or the scan cell order. The latter is mainly based on power-constrained test scheduling algorithms.^11–20 The system-level DFT limits the concurrency of the core tests based on a chip-level maximum allowable power limit. The power minimization problem is oriented toward reducing the switching activity in the circuit so that the dynamic power can be controlled. Although minimizing power consumption may reduce the overall temperature of the circuit under test (CUT), it is not effective enough in providing the best solution for peak temperature minimization on hotspots. Majority of these techniques failed to create spatially uniform temperature distribution due to non-uniform spatial power distribution.

In this paper, the importance of achieving spatial uniformity in temperature distribution and reducing the peak temperature is discussed. The temperature of a block depends on its own power density, as well as the heat transfer or heat exchange between the neighboring blocks. When the power consumption is uniformly distributed across the chip, thermal variance across the chip can be minimized. Therefore, genetic algorithm (GA)-based framework is proposed to fill don’t care bits in test patterns in such a way that both thermal variance across the chip and peak temperature are minimized.

The remainder of this paper is organized as follows. Section “Background and related work” reviews the background and related works. In section “Thermal modeling,” the thermal model is presented. The proposed GA-based thermal-aware don’t care filling algorithm is described in section “GA for thermal-aware patterns.” Experimental results of several ISCAS89 benchmark circuits are discussed in section “Results and discussion.” In section “Conclusion,” the conclusions are summarized.

Background and related work

Many low-power test generation techniques have been extensively investigated to minimize the power consumption during testing. However, the limiting power dissipation cannot alone guarantee against thermal hotspots. So power-aware testing has failed to solve the limitations. In order to solve the problem, thermal-aware strategies have to be developed.

Peak-temperature aware scan-vector optimization (PEAKASO) algorithm of Cho and Pan³ minimizes the peak temperature by scan vector reordering based on overheat pre-compensation. They proposed a window-based power analysis to predict hotspots in the CUT by considering power consumption of the block and its neighboring blocks. The peak temperature on the hotspot is minimized by ordering high-power-consuming patterns earlier to maximize the heat dissipation, reducing the heat generation and pre-compensating the overheat.

Rosinger et al.¹⁸ proposed a thermo-resistance model as a guide for test scheduling. They used the RC-equivalent (Resistance-Capacitance) architecture-level thermal model from Skadron et al.²¹ which makes use of the duality between the thermal and electrical phenomena. They only considered the lateral flow of heat from an active core by reducing a chip into a network of thermal resistances and thermal capacitances. The proposed test scheduling method used a clique cover algorithm over a resource conflict graph (RCG) to obtain thermal-safe test sessions. They computed thermal profiles quickly but with less accuracy.

The technique proposed by Rosinger et al.⁵ computes short thermal-safe test schedules. The authors suggested an approach that utilizes the core adjacency information to guide test scheduling. They also indicated that the non-uniform distribution of the heat results in hotspot on the die. Although the methods proposed in Cho and Pan³ and Rosinger et al.⁵ reduce the peak temperature on the hotspots, the temperature differences within the circuit range from 40 °C to 50 °C. The method is computationally expensive for complex systems.

Yoneda et al.²² proposed a thermal uniformity–aware X-filling technique to achieve a spatial uniform temperature distribution for high-quality at-speed testing. The objective of the method is to minimize the statistical variation in power density for each test pattern among the circuit blocks. They also proposed a test pattern reordering technique²³ that reduces the temporal temperature variation while maintaining the spatial temperature variation by their earlier method.

Dutta et al.²⁴ proposed a thermal-aware X-filling technique that properly assigns logic values to the X-bits to minimize the peak temperature as well as the thermal variance across the chip.

Thermal modeling

Thermal modeling techniques can estimate the temperature of a chip. There exists a well-known duality between heat transfer and electrical phenomena presented in Skadron et al.²¹ The heat transfer in a system can take place in three modes such as conduction, convection and radiation. In the electronic components, heat usually propagates through conduction which is assumed to be one dimensional (1D; Figure 1).

Figure 1.

One-dimensional heat conduction flow.

The 1D heat conduction in a homogeneous isotropic material is described as

q = - k \frac{d T}{d x}

(1)

where q is the heat flux in W/m², k is the thermal conductivity of the material in W/m K and T is the temperature in K. The heat flux is directly proportional to the temperature gradient at that point. The negative sign indicates that the heat flows in the direction of decreasing temperature.

Equation (1) can be rewritten as

Q = - k A \frac{T_{2} - T_{1}}{L}

(2)

where $Q = A q$ with Q being the heat transfer rate and A being the heat conducting area. Thermal resistance is written as

R_{t h} = \frac{T_{2} - T_{1}}{A} = \frac{L}{k A}

(3)

There is a resemblance between equation (3) and Ohm’s law in circuit theory

R = \frac{V_{2} - V_{1}}{I} = ρ \frac{L}{A}

(4)

Heat conduction is also a transient process. The temperature distribution of an IC is governed by the heat conduction equation

ρ c_{p} \frac{\partial T (x, y, z, t)}{\partial t} = k \nabla^{2} T (x, y, z) + g (x, y, z, t)

(5)

where T refers to variation in temperature with respect to time (K), ρ specifies material density (kg/m³), k denotes thermal conductivity (W/m K), g represents volume power density parameter depending on time (W/m³) and c_p is the specific heat (J/kg K). Both g and k are assumed as constants. Equation (5) can be written in 1D form and can be integrated on both sides by x from 0 to L

(ρ c_{p} A L) \frac{d T (t)}{d t} = k A \frac{Δ T (t)}{L} + Q

(6)

where ΔT = T₂ – T₁. The first term of the right-hand side of equation (6) is the heat transferred through thermal resistance. The equation can be rearranged as

C_{t h} \frac{d T (t)}{d t} + \frac{T_{2} - T_{1}}{R_{t h}} = Q

(7)

where $C_{t h} = ρ c_{p} A L = ρ c_{p} V$ with V being the volume of the material. The first term on the left-hand side of equation (7) resembles the following equation

C \frac{d V (t)}{d t} = i c (t)

(8)

Thermal capacitance is the capability of the material to absorb heat, while electrical capacitance is the capacity of the material to store electrical charge. Equation (7) states that the total heat flowing through the material is equal to the sum of the heat flowing through the thermal capacitance (the alternative current (AC) component) and the heat flowing through the thermal resistance (the direct current (DC) component; Table 1).

Table 1.

The duality between thermal and electrical phenomenon.

Thermal quantity	Electrical quantity
Heat transfer rate Q	Current I
Temperature difference T	Voltage difference V
Thermal resistance R_th	Resistance R
Thermal capacitance C_th	Capacitance C

Using thermal resistance and thermal capacitance of each sub-block in the package, an equivalent electric circuit is derived from modeling the dynamic heat flow in the chip. The dissipated power and layout (floor plan) information of the blocks is given as an input to the thermal model at every time step. The average temperature of each block over the time interval is estimated using computational methods.

GA for thermal-aware patterns

GAs²⁵ constitute a class of heuristic search and optimization techniques based on the principles of natural selection and genetics. They have been applied in various domains that are traditionally difficult to optimize. GAs can identify globally optimal or suboptimal solutions within reasonable time and computational cost. GA handles a population of potential solutions to a given problem. Each represents a possible solution (chromosome) to the problem and is evaluated by a fitness function to assess its competence to survive in the next generation. The fittest chromosomes are given opportunities to reproduce with individuals in the population. This produces new individuals as “offspring.” As this process continues, a sequence of successive generations evolves, and the average fitness of the chromosomes tends to increase until the termination criterion is satisfied. Since highly fit individuals are more likely to be selected as parents, the most promising areas of the search space are explored. If the GA has been designed correctly, the population will converge to an optimal solution to the problem.

Since the objective of the problem is to minimize the peak temperature of the circuit during testing, the power density variance across the block is found and tried to be minimized. The large test set with reasonable don’t care bits generated using MinTest²⁶ is taken as an input for testing the CUT. The GA is useful when the search space is very large. So, GA is chosen for the problem of finding an appropriate filling of the don’t care bits which will lead to peak temperature reduction.

In order to apply a GA for peak temperature reduction and thermal variation reduction, it is necessary to define an individual solution representation, selection procedure, crossover operator, mutation operator and fitness function. The GA procedure is outlined in Figure 2.

Figure 2.

Flow diagram of GA-based thermal-aware test pattern generation.

Genotype

The genotype of a problem is the representation of an individual in the GA. For the experimentation, the test sets with don’t care bits generated using MinTest have been used. In this problem, the structure of the chromosome is x₀, x₁, x₂, …, x_n – 1, where n is the number of don’t care bits in one test pattern. Each x_i can be either “0” or “1.” The don’t care bits in a test pattern are randomly filled using GA. A random number of chromosomes are produced to form the initial population. Two special vectors (all 0s and all 1s) that are corresponding to 0-fill and 1-fill are included in the initial population so that the result does not degrade below the value given all 0-fill and 1-fill algorithms.

Genetic operators

Genetic operators have been used in GAs to generate diversity and to combine existing solution. Direct copy, crossover and mutation have been used to evolve the new generations.

Crossover

Chromosomes from the population are selected as parents. The selection of parents involving in crossover has been biased toward the better fit chromosomes. A certain percentage (here 20%) of the population with minimum power density variance and minimum overall power (both static and dynamic) is considered to form the “best class.”²⁷ To carefully choose a chromosome for crossover, first a random number between 0 and 1 is generated. If the number is greater than 0.5, a chromosome from the best class is selected. Otherwise, a chromosome is chosen from the entire population. The procedure increases the probability of a better fit offspring getting selected. Similarly, the other parent gets selected.

After selecting two parent chromosomes, the new offspring are generated using the following procedure:

procedure offspring_gen (P₁, P₂)
begin
for i = 1 to n do
Generate a random number r1 between 0 and 1
if (r1 > 0.5)
O₁[i] ← P₁[i];
O₂[i] ← P₂[i];
Else
O₁[i] ← P₂[i];
O₂[i] ← P₁[i];
end if
i = i + 1
end for
end

The newly generated offspring are checked for their uniqueness.

Mutation

Mutation is intended to maintain sufficient genetic diversity from one generation to the next. Mutation helped to prevent the algorithm from being trapped in a local minimum. First, two random numbers (r1 and r2) are generated between 1 and the width of the chromosome. The entries are toggled between the two positions. The resulting chromosome is modified to satisfy the uniqueness criteria. Here, we have taken the mutation rate as 10% of the total population.

Direct copy

The best chromosomes (possibly 20% of the total population) of every generation are copied to the next so that the possibility of degradation between the generations through a genetic operator is eliminated.

Termination

The GA process will terminate if there is no improvement in the best fitness of the population over that past 30 generations.

Fitness calculation

In order to carry out optimization using GA, a suitable fitness function has to be formulated to rank the chromosomes in a particular generation. In this work, the fitness function is formulated to reduce peak temperature and thermal variance as well as power consumption across the chip. The entire circuit is partitioned into a number of blocks. Each block contains flip-flops and several gates. In scan-based designs, test application is carried out by simultaneous scan-out current responses and scan-in of the next test pattern, and this process is repeated until all the test patterns are applied. During the scan-out and scan-in operations, many intermediate patterns are generated. These ripple patterns consume large power.

The objective of this work is to minimize the variance in power density between the blocks. In addition to that, the overall power consumption should be minimized. The variance S2 in power density for each test pattern t is defined as follows to analyze the spatial variation

S 2 = \frac{1}{N} \sum_{i - 1}^{N} {(P D_{i} - P D_{a v g})}^{2}

(9)

P_{o v e r a l l} \leq minimum power (1 - fill, 0 - fill, MT - fill)

(10)

where N is the number of layout blocks for temperature analysis, PD_i is the power density in block b_i for each test pattern t, PD_avg is the average power consumption among all the blocks for each test pattern t, P_overall is the total power consumption (dynamic and static power) for each test pattern t and MT-fill is the minimum transition fill for each test pattern t.

Results and discussion

This section presents the results of experimentation with ISCAS89 benchmark circuits. The test sets generated using MinTest ATPG program have been utilized for the experiments. The characteristics of the MinTest test profile for ISCAS89 benchmarks are presented in Table 2.

Table 2.

Test set profile for ISCAS89 benchmark circuits using MinTest ATPG program.

Circuit	Primary inputs	Scan cells	Number of gates	Test vectors	Size of T_D	%X-bits
S5378	35	179	2779	111	23,754	72.62
S9234	36	211	5597	159	39,273	73.01
S13207	62	638	7951	236	165,200	93.15
S15850	77	534	9772	126	76,986	83.55

Thermal simulation

Thermal simulation was used to estimate the power and temperature distribution across the block. The thermal simulation²⁸ steps are as follows:

Verilog circuit description is fed to the Synopsys Design Vision²⁹ to generate a gate-level netlist.

All normal flip-flops are converted into scan flip-flops using the Synopsys DFT Compiler.³⁰

IC Compiler³¹ from Synopsys is used to create the floor plan of the scan inserted design using standard cell library. Scan netlist and the test patterns are used to estimate the power. The power consumption of each of the logic elements (gates and flip-flops) with different types and inputs is estimated using the Synopsys Design Vision tool and stored in a database. This database is used to convert the transitions in individual logic elements to their corresponding power values during circuit simulation for each scan shift and capture operation.

Synopsys IC Compiler is used to obtain floor plan information. The floor plan is divided into some blocks for thermal simulation. Power trace values are estimated for each of these blocks.

HotSpot, a thermal simulation tool, is used to perform thermal simulations. HotSpot takes power trace and block-level floor plan as inputs (Table 3).

Table 3.

HotSpot parameters used for thermal simulation.

Chip specifications (Silicon)
Chip thickness (m)	0.00015
Silicon thermal conductivity (W/(m K))	100.0
Silicon specific heat (J/(m³ K))	1.75e6
Temperature threshold for DTM (Dynamic Thermal Management) (K)	354.95
Heat sink specs (aluminum alloy)
Convection capacitance (J/K)	140.4
Convection resistance (K/W)	0.1
Heat sink side (m)	0.06
Heat sink thickness (m)	0.0069
Heat sink thermal conductivity (W/(m K))	400.0
Heat sink specific heat (J/(m³ K))	3.55e6
Heat spreader specs (aluminum alloy)
Spreader side (m)	0.03
Spreader thickness (m)	0.001
Heat spreader thermal conductivity (W/(m K))	400.0
Heat spreader specific heat (J/(m³ K))	3.55e6
Interface material specs
Interface material thickness (m)	2.0e–5
Interface material thermal conductivity (W/(m K))	4.0
Interface material specific heat (J/(m³ K))	4.0e6

Observation

Power consumption

Table 4 shows the percentage reduction in power variance, average power and peak power, respectively. ΔV_pwr is the relative difference in power density variance, ΔP_avg is the relative difference in the average power and ΔP_peak is the relative difference in peak power. The relative difference in power density variance is computed as $((V_{e x i s} - V_{p r o p}) / V_{e x i s}) \times 100$ , where V_exis and V_prop denote the power variance calculated by the existing and the proposed X-filling techniques, respectively. The relative differences in the average power and in peak power are computed in a similar manner.

Table 4.

Percentage reduction in power variance, average power and peak power: comparison with other methods.

Circuit	Percentage reduction in power variance, average power and peak power
	0-fill			1-fill			MT-fill
	ΔV_pwr (%)	ΔP_avg (%)	ΔP_peak (%)	ΔV_pwr (%)	ΔP_avg (%)	ΔP_peak (%)	ΔV_pwr (%)	ΔP_avg (%)	ΔP_peak (%)
S5378	27.74	8.29	4.25	21.91	20.33	21.64	24.56	2.06	0.49
S9234	66.95	82.21	82.21	71.16	83.32	84.71	69.72	91.49	93.86
S15850	37.02	68.38	18.50	85.29	82.88	46.93	78.24	87.11	68.77
S13207	40.56	38.39	36.04	86.53	85.98	82.28	81.67	88.32	86.12
Average	43.06	49.31	35.25	66.22	68.12	58.89	63.55	67.24	62.31

MT: minimum transition.

The results were obtained by an incompletely specified test set filled with known 0-fill, 1-fill and MT-fill and they were compared with the results of the proposed strategy. The results demonstrate that a significant reduction in spatial power density variance was obtained using the proposed X-filling method. In comparison with the various X-filling such as 0-fill, 1-fill and MT-fill, the proposed method achieved up to 43%, 66% and 64% reduction on average in power density variance, respectively. The proposed method also achieved up to 49%, 68% and 67% reduction on average in the average power when compared with 0-fill, 1-fill and MT-fill, respectively. The proposed method achieved up to 35%, 59% and 62% reduction on average in peak power when compared with 0-fill, 1-fill and MT-fill, respectively.

Yoneda et al.²² achieved on average a reasonable reduction in power variance compared to low-power-oriented techniques such as 0-fill, 1-fill and MT-fill. They also mentioned that the method of Yoneda et al.²² incurred around 35% increase in overall average power consumption. But our approach outperforms the low-power-oriented techniques by 49%–68% in average power consumption.

Temperature

Table 5 shows the peak temperature values obtained by thermal simulation using HotSpot. Table 6 shows the corresponding percentage reduction in thermal variance. Table 7 shows the corresponding percentage reduction in temperature. ΔV_temp is the relative difference in peak temperature and ΔV_ther is the relative difference in thermal variance. The relative differences in peak temperature and in thermal variance are computed in a similar manner to ΔV_pwr. The results demonstrate that a significant reduction in spatial thermal variance was obtained using the proposed X-filling method. In comparison with 0-fill, 1-fill and MT-fill, the proposed method achieved not only 45%, 64% and 56% reduction in thermal variance but also 18%, 28% and 26% reduction in peak temperature, respectively.

Table 5.

Peak temperature: comparison with other methods.

Circuit	Peak temperature (K)
Circuit	0-fill	1-fill	MT-fill	Yoneda et al.²²	Dutta et al.²⁴	GA-FILL (proposed method)
S5378	528.50	492.71	498.21	501.28	468.26	449.37
S9234	574.26	621.42	598.66	552.31	502.22	472.04
S15850	432.52	586.62	567.25	421.73	412.34	373.09
S13207	477.44	595.79	558.80	402.23	373.62	350.86

MT: minimum transition; GA: genetic algorithm.

Table 6.

Percentage reduction in thermal variance: comparison with other methods.

Circuit	Percentage reduction in peak thermal variance
	0-fill	1-fill	MT-fill	Yoneda et al.²²	Dutta et al.²⁴
	ΔV_ther (%)	ΔV_ther (%)	ΔV_ther (%)	ΔV_ther (%)	ΔV_ther (%)
S5378	35.79	14.42	17.21	22.21	12.35
S9234	71.86	79.95	61.23	21.54	14.26
S15850	34.67	81.23	72.21	23.26	16.21
S13207	38.78	79.34	71.93	26.56	15.64
Average	45.28	63.74	55.65	23.39	14.62

MT: minimum transition.

Table 7.

Percentage reduction in peak temperature: comparison with other methods.

Circuit	Percentage reduction in peak temperature
	0-fill	1-fill	MT-fill	Yoneda et al.²²	Dutta et al.²⁴
	ΔV_temp (%)	ΔV_temp (%)	ΔV_temp (%)	ΔV_temp (%)	ΔV_temp (%)
S5378	14.97	8.80	9.80	10.36	4.03
S9234	17.80	24.04	21.15	14.53	6.01
S15850	13.74	36.40	34.23	11.53	9.52
S13207	26.51	41.11	37.21	12.77	6.09
Average	18.25	27.58	25.59	12.30	6.41

MT: minimum transition.

In comparison with Dutta et al.,²⁴ peak temperature has been reduced 4%–10% in our approach. In comparison with Yoneda et al.,²² peak temperature has been reduced 10%–15% in our approach. This is happening because the existing approach has considered only limited patterns. But the proposed method has considered reasonable patterns so that the peak temperature has been reduced.

The improvements obtained in the proposed case due to the power density variance among the blocks were minimized. The results also show that the peak temperature strongly depends on power distribution and the proposed method effectively minimizes the power density variance. So the peak temperature is minimized.

Conclusion

In this paper, a GA-based don’t care filling technique is proposed to deal with peak temperature minimization in deep submicron technologies. The main contribution of the algorithm is to fill the don’t care bits with a proper value (0 or 1) to reduce the spatial power density variance and temperature variance across the chip during manufacturing testing. The experimental results show that GA-based don’t care filling technique is more effective to minimize temperature and thermal variance while preserving the average power relatively at low level.

Footnotes

Declaration of conflicting interests

The author(s) declared no potential conflicts of interest with respect to the research, authorship and/or publication of this article.

Ethical approval

This article does not contain any studies with human participants or animals performed by any of the authors.

Funding

The author(s) received no financial support for the research, authorship and/or publication of this article.

Informed consent

Informed consent was obtained from all individual participants included in the study.

References

Girard

Survey of low-power testing of VLSI circuits. IEEE Des Test Comput 2002; 19(3): 82–92.

Basker

Arulmurugan

Survey of low power testing of VLSI circuits. In: Proceedings of the international conference on computer communication and informatics, Coimbatore, India, 10–12 January 2012, pp. 1–7. New York: IEEE.

Cho

Pan

DZ.

PEAKASO: peak-temperature aware scan-vector optimization. In: Proceedings of the 24th VLSI test symposium, Berkeley, CA, 30 April–4 May 2006, pp. 52–57. New York: IEEE.

Girard

Nicolici

Wen

Power-aware testing and test strategies for low power devices. Springer Science & Business Media, New York, USA, 2010.

Rosinger

Al-Hashimi

Chakrabarty

Thermal-safe test scheduling for core-based system-on-chip integrated circuits. IEEE T Comput Aid D 2006; 25(11): 2502–2512.

Rosinger

Al-Hashimi

Nicolici

Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction. IEEE T Comput Aid D 2004; 23(7): 1142–1153.

Saxena

Butler

Whetsel

An analysis of power reduction techniques in scan testing. In: Proceedings of the international test conference, Baltimore, MD, 1 November 2001, pp. 670–677. New York: IEEE.

Flores

Costa

Neto

et al . Assignment and reordering of incompletely specified pattern sequences targeting minimum power dissipation. In: Proceedings of the 12th international conference on VLSI design, 7–10 January 1999, pp. 37–41, Goa, India: IEEE.

Girard

Landrault

Pravossoudovitch

et al . Reduction of power consumption during test application by test vector ordering [VLSI circuits]. Electron Lett 1997; 33(21): 1752–1754.

10.

Wang

Gupta

SK.

ATPG for heat dissipation minimization during test application. IEEE T Comput 1998; 47(2): 256–262.

11.

Chou

Saluja

Agrawal

VD.

Scheduling tests for VLSI systems under power constraints. IEEE T VLSI Syst 1997; 5(2): 175–185.

12.

Muresan

Wang

Vladutiu

A comparison of classical scheduling approaches in power-constrained block-test scheduling. In: Proceedings of the international test conference, Atlantic City, NJ, 3–5 October 2000, pp. 882–891. New York: IEEE.

13.

Nicolici

Al-Hashimi

BM.

Power conscious test synthesis and scheduling for BIST RTL data paths. In: Proceedings of the international test conference, Atlantic City, NJ, 3–5 October 2000, pp. 662–671. New York: IEEE.

14.

Larsson

Arvidsson

Fujiwara

et al . Efficient test solutions for core-based designs. IEEE T Comput Aid D 2004; 23(5): 758–775.

15.

Iyengar

Chakrabarty

System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints. IEEE T Comput Aid D 2002; 21(9): 1088–1094.

16.

Chakrabarty

Design of system-on-a-chip test access architectures using integer linear programming. In: Proceedings of the 18th VLSI test symposium, Montreal, QC, Canada, 30 April–4 May 2000, pp. 127–134. New York: IEEE.

17.

Ravikumar

Chandra

Verma

Simultaneous module selection and scheduling for power-constrained testing of core based systems. In: Proceedings of the 13th international conference on VLSI design, Calcutta, India, 3–7 January 2000, pp. 462–467. New York: IEEE.

18.

Rosinger

Al-Hashimi

Chakrabarty

Rapid generation of thermal-safe test schedules. In: Proceedings of the conference on design, automation and test in Europe (Volume 2), Munich, 7–11 March 2005, pp. 840–845. New York: IEEE.

19.

Aghaee

Peng

Eles

Process-variation and temperature aware SoC test scheduling technique. J Electron Test 2013; 29(4): 499–520.

20.

Peng

Eles

et al . Thermal-aware SoC test scheduling with test set partitioning and interleaving. J Electron Test 2008; 24(1–3): 247–257.

21.

Skadron

Stan

Huang

et al . Temperature-aware microarchitecture. In: Proceedings of the 30th annual international symposium on computer architecture, San Diego, CA, 9–11 June 2003, pp. 2–13. New York: IEEE.

22.

Yoneda

Inoue

Sato

et al . Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing. In: Proceedings of the 28th VLSI test symposium, Santa Cruz, CA, 19–22 April 2010, pp. 188–193. New York: IEEE.

23.

Yoneda

Nakao

Inoue

et al . Temperature-variation-aware test pattern optimization. In: Proceedings of the 16th European test symposium, Trondheim, 23–27 May 2011, pp. 214–214. New York: IEEE.

24.

Dutta

Kundu

Chattopadhyay

Thermal aware don’t care filling to reduce peak temperature and thermal variance during testing. In: Proceedings of the 22nd Asian test symposium, Yilan City, Taiwan, 18–21 November 2013, pp. 25–30. New York: IEEE.

25.

Golberg

DE.

Genetic algorithms in search, optimization, and machine learning. Addison-Wesley, 1989, Boston, MA, USA.

26.

Hamzaoglu

Patel

JH.

Test set compaction algorithms for combinational circuits. In: Proceedings of the international conference on computer-aided design, San Jose, CA, 8–12 November 1998, pp. 283–289. New York: ACM.

27.

Chattopadhyay

Choudhary

Genetic algorithm based approach for low power combinational circuit testing. In: Proceedings of the 16th international conference on VLSI design, New Delhi, India, 4–8 January 2003, pp. 552–557. New York: IEEE.

28.

Karmakar

Chattopadhyay

Thermal-aware test data compression using dictionary based coding. In: Proceedings of the 28th international conference on VLSI design, Bangalore, India, 3–7 January 2015, pp. 53–58. New York: IEEE.

29.

Synopsys Design Vision UserGuide (DVUG), Version D (2010) SP2.

30.

Synopsys DFT Compiler Scan Userguide (DCSU), Version C (2009).

31.

Synopsys

Compiler user guide (2013).

Genetic Algorithm-based thermal uniformity–aware X-filling to reduce peak temperature during testing

Abstract

Keywords

Introduction

Background and related work

Thermal modeling

GA for thermal-aware patterns

Genotype

Genetic operators

Crossover

Mutation

Direct copy

Termination

Fitness calculation

Results and discussion

Thermal simulation

Observation

Power consumption

Temperature

Conclusion

Footnotes

Declaration of conflicting interests

Ethical approval

Funding

Informed consent

References