YangN.HensonW. K.HauserJ. R.WortmanJ. J., “Modeling Study of Ultrathin Gate Oxides Using Direct Tunneling Current and Capacitance-Voltage Measurements in MOS Devices,”IEEE Trans. on Electron Devices, vol. 46, p. 1464, July 1999.
2.
SchuegrafK.F., “Impact of Polysilicon Depletion in Thin Oxide MOS Technology,”Proc. VLSI-TSA, p. 86, 1993.
3.
ShiY.MaT. P.PrasadS.DhandaS., “Polarity-dependent tunneling current and oxide breakdown in dual-gate CMOSFETs,”Electronics Device Lett., vol. 19, p. 391, Oct. 1998.
4.
ChoiC. H., “Capacitance reconstruction from measured C-V in high leakage, nitride/oxide MOS,”IEEE Trans. on Electron Devices, vol. 47, p. 1843, Oct. 2000.
5.
YangK. J.HuC.M., “ MOS Capacitance Measurements for High-Leakage Thin Dielectrics,”IEEE Trans. on Electron Devices, vol. 46, p. 1500, July 1999.
6.
BarlageD. W., “Inversion MOS Capacitance Extraction for High-Leakage Dielectrics Using a Transmission Line Equivalent Circuit,”IEEE Electron Device Letters, vol. 21, p. 454, Sept. 2000.
7.
SutoH., “Methodology for Accurate C-V Measurement of Gate Insulators below 1.5nm EOT,” Extended Abstract of the 2002 International Conf. On Solid State Devices and Materials, p. 748, 2002.
8.
OkawaY.NorimatsuH.SutoH.TakayanagiM., “The Negative Capacitance Effect on the C-V measurement of Ultra Thin Gate Dielectrics Induced by the Stray Capacitance of the Measurement System,”Proc. ICMTS, p. 197, 2003.
9.
AhmedK., “Impact of Tunnel Currents and Channel Resistance on the Characterization of Channel Inversion Layer Charge and Polysilicon-Gate Depletion of Sub-20Å Gate Oxide MOSFETs,”IEEE Trans. on Electron Devices, vol. 46, p. 1650, 1999.
10.
ChoH.BurkD., “A Three-Step Method for the De-Embedding of High Frequency S-Parameter Measurements,”IEEE Trans. on Electron Devices, vol. 38, p. 1371, June 1991.
11.
SchmitzJ., “Test Structure Design Considerations for RF-CV Measurements on Leaky Dielectrics,”Proc. ICMTS, p. 181, 2003.
