Abstract
Field bus system has been successfully introduced into industrial automation. Nowadays, most of the motion control bus is based on the Ethernet physical layer, and all of the new standards are based on the Ethernet physical layer. This paper introduces a new optimized technology based on motion control bus of the Ethernet physical layer, which includes the prediction mechanism in the arrival of the frames, the retransmission mechanism in advance, and a new mechanism of independent verification of data segment. Tests show that using the mechanisms in this paper can enhance efficiency and reliability in communication process.
1. Introduction
In recent years, international advanced NC machine and control system of industrial robot all have used motion control bus to connect controller, servo and I/O equipment, and so forth. Motion control system based on motion control bus has advantages of freely amending hardware configuration, easily achieving distributed control, and reliability and higher control system accuracy.
Recently, most of the motion control bus is based on RS485 and Ethernet physical layer, and all of the new standards are based on Ethernet physical layer; typical examples are from MECHATROLINK II to MECHATROLINK-III, from SERCOS II to SERCOS III, and from CC-Link to CC-Link IE, all of them have changed into Ethernet physical layer from the RS485 physical layer of the last generation; it is a common sense to use Ethernet physical layer as a new generation of physical layer of motion control bus. NC machines and control system of industrial robots have different control requirements in the field bus contrasted by ordinary control system. Generally speaking, the motion control system has requirements for synchronization and real time that is, to say, the synchronous cycle is at least 1 ms, and synchronous jitter is at least 1 μs [1]. But original function of Ethernet is not designed for the field bus, so different field bus standards generally take some transformations which are based on typical Ethernet. From the view of means of transformation, this can basically be divided into two categories
(1)Pure software type. It is characterized by increasing real time [2–5] through changing network protocol stack [6], system software of slave station, or scheduling method of switch. This method does not need to change existing hardware and has become one of hot spots [7, 8] because of the lowest cost and the fastest implement, but its synchronization performance and real-time performance are at the worst. In the academic research literature, synchronous cycle of pure software is about 1 ms or so, and in the different open industry standard, synchronization cycle is always 5 ms [9–11] or so. Among them, the best real-time performance is Ethernet Powerlink; it uses a concentrator rather than a switch to avoid delay in the exchange process; that is to say, by using bus topology, it avoids delaying problem of star structure switch, making synchronization cycle up to 200 μs and synchronization jitter up to 1 μs [12], but its bus structures also limit transmission efficiency and performance of synchronization and real-time decreases along with the increase in the number of slave stations [13].
(2)Soft and hard combination type. It is characterized by changing MAC layer of slaves station and using the special ASIC chip or FPGA to accelerate its receiver and transmission speed of slave station; the typical method includes EtherCAT, SERCOSIII, Profinet IRT, MECHATROLINK-III, and RTEX. All of their synchronization cycle can reach less than 100 μs and synchronization jitter can reach less than 1 μs.
Except for the two above-mentioned transformation methods, in recent years, popular IEEE1588 standard [14] can also provide rather good performance of synchronous jitter.
Seen from the comparison of each the above-mentioned of technical routes, the method of pure software type has poor performance and cannot meet the requirements in the real time, so if we use the EtherCAT and the chip SERCOS III based on both ordinary Ethernet physical layer and transform solutions of the link layer, it will be the most suitable in CNC machine and industrial robot control system.
The research on program of transformation of the link layer is being widely and deeply carried out in foreign countries. In 2007, Jasperneite et al. carried out a detailed analysis and comparison of performance and potential about EtherCAT and Profinet IRT [15]. In 2008, Prytz made a detailed comparison between synchronization performance and real-time performance about EtherCAT and Profinet IRT [16]. At the same year, Schumacher et al. made some intensive research on Profinet IRT, putting forward IRT+ protocol based on mode of IRT; his optimized methods included optimization of frame preamble and optimization of different data organization mode from upstream data and downstream data, which was of great value [17]. In 2010, Cena et al. made an analysis for real-time performance [18]. At the same year, Gunzinger et al. made a research on optimization in real-time performance of Profinet IRT and achieved it by using FPGA [19]. From 2010 to 2011, Knezic et al. made an optimization on upper layer protocol of EtherCAT [20] and made an analysis on network topology of EtherCAT [21].
2. Research on Synchronization
Realization mechanism of the IEEE1588 is complex, and its cost is much high, although its synchronous jitter performance (8 ns) is much better than that of the EtherCAT (20 ns), but because of the increase in relative cost, the significance of improvement in this performance is limited for the motion control system. For the ordinary motion control systems, requirements can be met in 8 ns synchronous jitter of SERCOS III, but realization process of the EtherCAT mechanism is still too complex; the function from complex clock system of the EtherCAT mechanism is limited in NC machines and industrial robots system.
Timing completion of calculation results are determined by characteristics of data sampling interpolation methods, and timing repeat is also determined in the process of communication, so synchronous mechanism of SERCOS III depending on the data frame that is timed and sent is very appropriate here. But because of uncertainty of delay in the processing of data received by the Ethernet physical layer chip, synchronization mechanism of SERCOS III in slave station is much more difficult to reliably work at most times.
2.1. Analysis of Crucial Question of Synchronization Mechanism
Uncertainty cannot be avoided in receiving delay process, while ordinary Ethernet PHY chip handles Ethernet frames. This reason caused by uncertainty differs from different work mode of PHY chip. The work mode includes standard MII mode and RMII mode. Under MII's mode and RMII's mode, although delay fluctuation appears in different positions, the results are the same, and this delay fluctuation will constantly expand along with the Ethernet frames spreading in the slave station. By finding of actual measurement and simulation calculation of delay transmission, delay fluctuation is in line with binomial distribution. According to analysis of the simulation results, delay fluctuation of the farthest slave station will continually expand along with increase in network and slave station number, which has serious impact on synchronous ability of the whole network.
2.2. Mechanism for the Arrival of Prediction
In order to solve cumulative problem in delay fluctuations along with the increase in sequence number of slave station, the prediction mechanism in the arrival of frames is used in this paper to revise start time of timer, when delay fluctuation is larger, which make timer start at reasonable time and obtain more stable synchronous signal.
In order to predict the moment of the arrival of frames, firstly we need to get ideal time at the arrival of communicating frames, and then use this moment as time origin and calculate the arrival time of subsequent frames by communication cycle.
The process in the implement in prediction of the arrival of slave station is shown in Figure 1 as follows.
Timing diagram of predicting the arrival mechanism.
(1) First communication cycle clocked will be told to slave station by master station, this communication stage set is t1, then subsequent and respective communication stages are t2, t3, t4, ….
(2) When slave station receives communication cycle at stage t1, counter C p will start to count.
(3) Another counter C f is started by slave station in stage t2 and starts to count at the same time. When frames are actually received, C p is recorded as C px , counter value transformed by communication cycle is recorded as C t , the difference of C px and C t is recorded as C p t, and counter value arrival predicted in next time is recorded as C o and its value set as Cpt.lim. From the start of communication stage between t2 and t2 later, the interval time to receive the next frame is predicted when frame is received every time; the calculation method is shown as follows: if C pt is larger than Cpt.lim, then (C t + Cpt.lim) will be decreased when C p is counting at the same time, and C o is set as (C t + Cpt.lim); if C pt is smaller than Cpt.lim, then (C t + Cpt.lim) will be decreased when C p is counting at the same time, and C o is set as (C t + Cpt.lim) if the range of C pt is from negative Cpt.lim and positive Cpt.lim, C t will be decreased when C p is counting at the same time, and C o is set as C t .
(4) Within stage t3 and its later stage, when count value C f reaches value C o obtained by the calculation of the upper stage, signal will be reached by frames which generate prediction, and at the same time the frames themselves will be cleared to start counting from 0. That arrival signal obtained by prediction from frames by every time is considered as arrival signal from actual frames will start timer that generates synchronous signal and will generate synchronous signal as SERCOS II's mechanism of generating synchronous signal. Because of the situation that there are two timers in SERCOS II's mechanism, slave station needs to provide a forecast system for every timer.
In the above-mentioned prediction of the arrival moment of frames, the smaller the value of Cpt.lim, the better it will be, but the condition must be met as follows:
Thereinto, F s is clock cycle of slave station, and S r is relative drift difference value for clock between master station and slave station. If Cpt.lim degenerates to 0, the interval of predicted arrival moment from slave station will become C t , losing compensation function for the clock drift. Because of the situation that Cpt.lim cannot be decimal, minimum of Cpt.lim will be less than 1 with the reduction of T, so finally in case of the situation that the value will be less than 1, value of Cpt.lim will be 1.
Figure 2 (a) is fluctuation simulation waveforms of actual arrival interval frames of the twenty-fourth slave station when F s is 50 MHz, and Figure 2 (b) is fluctuation simulation waveforms of interval of predicted arrival moment of the station. Fluctuations of 480 ns can be reduced to the range of 160 ns by using testing mechanism at the same time jitter of predicted arrival moment that is only 160 ns.
Simulation comparison of arrival prediction mechanism of 24th slave station.
According to the simulation results of slave station which ranges from 1 to 48, when F s is 50 MHz, jitter of actual arrival moment of four previous slave stations is within 160 ns; jitter will begin to constantly increase from the fifth slave station, and jitter of the predicted arrival moment can be controlled within 160 ns all the way.
There is a small probability that the interval of actual arrival moment of frames is more than 400 ns, there is no way to provide comparative effect in prediction mechanism under such situation, but according to the analysis from the view of qualitative point, it is assumed that arrival moment of a frame is severely later, which is closer to the maximum of fluctuation interval, and according to the above-mentioned distribution rules, probability that next frame is similar with the situation is very small, therefore although the interval of the frame that is, severely hysteretic and the previous frame will be very large, but the interval of the frame and the next frame will be very small, which will completely be filtered out by integral low-pass filter. When value of Cpt.lim is 1 and F s is 100 MHz, even consecutive and serious lag is aroused in frames, which cause that the maximal fluctuation of delay is just m × 20 ns. This extreme situation can be dealt with by integral low-pass filter in the prediction mechanism too.
2.3. The Improvement of the Arrival of Prediction in Violent Interferential Environment
In some severe interference environment, MST telegrams of SERCOS III can also be interfered, and synchronous signal completely is lost by slave station at the same time. By using the above-mentioned mechanism for arrival of prediction in this article, even though the frames weren't completely received by slave station, synchronous signal can also be generated by slave station by means of keeping principle invariable and modifying slightly. The principle is shown as follows:
In the second step of prediction realization process of slave station, a new added counter is used for recording interval of frames, when value of C s is greater than value of Cs.max, it is considered that a frame is completely lost, at the same time, let us assume that a frame is received, and continues to run as original steps. Cs.max is maximum value of the internal of receiving frames in theory, n × 40 ns is the maximum value of the interval fluctuation of receiving frames from the nth slave station, Cs.max.n is Cs.max of the nth slave station, which is shown as follows:
If a frame is completely lost by detection, then when detection is performed again, we need to consider T × F s as value of Cs.max.n, because there has been judged on maximal lag when frames are lost by judgment in the first time, it is impossible that the maximum of the interval of the first lost frame and the second lost frame is greater than lagging mean T × F s .
3. Research on Real-Time
3.1. Limit of the Ethernet Protocol for the Transmission of Frames
The transition of straight-through principle can greatly improve efficiency of transmission of ring topology, but due to some of the Ethernet physical layer's requirements and the limitations of the physical layer chip, there is still space for efficient improvement in the field of motion control. Requirements and limitations are shown as follows:
There must be a minimum time interval between two separate Ethernet frames (front and back) in one line, we can call the minimum time interval as minimum interval between frames.
Ethernet frames have limit of minimum length. In order to avoid the problem in collisions, CSMA/CD mechanism is used in transmission protocol of standard Ethernet. The minimum length of frames is 64 bytes, which is ruled by transmission protocol of standard Ethernet.
3.2. Retransmission Mechanism in Advance
3.2.1. Contradictions of Real Time and Reliability
As for efficient research in normal communication condition, currently problems have been solved better by using lumped-frame direct forwarding principle, whose efficiency has been closed to limit in theory. From the view of the conditions of actual testing in this paper, as for bus using twisted-pair physical connection, under the conditions of severe electromagnetic interference, it is very common to see communication failure. As for the conditions of communication failure, the conditions can generally be dealt with by retransmission mechanism. As for master station, the paper notes that the network is idle in the period of time between the end of the first frame transmitted and the starting of retransmission of frames, and idle proportion will be increased, while the amount of datum from the slave station is smaller and transmission speed of the Ethernet is higher. The reason which causes larger idle is related to the delay of Ethernet physical layer chip.
3.2.2. Delay of Transceiver from Physical Layer Chip
As for Ethernet of 100 M, for example in NS Company's Ethernet PHY chip DP83848, the average of delay of transceiver is 590 ns by using RMII interface and cable of 0 m between transceiver stations, and average of the same delay is 310 ns by using MII interface and cable of 0 m between transceiver stations, but the signal is required for special processing while clock domains are crossed by it, because RX_CLK of MII mode is not synchronous with local clock, the process of processing itself is about four local clocks, for example, additional 80 ns is needed for local clock of 50 MHz. As for Ethernet of 1000 M, for example in NS Company's Ethernet PHY chip DP83848, according to the datum given by the data sheet, delay of transmission from GMII interface is 152 ns and delay of receiver from that is 386 ns; therefore, delay of transceiver is 536 ns. In conclusion, the set of delay of transceiver for every node is 0.5 μs, which is shown as t d .
3.2.3. Retransmission Mechanism in Advance
As for the situation of retransmission, since the retransmitted data itself does not depend on contents of the first data frame, frames can be retransmitted in advance in this idle time; that is to say, frames must be retransmitted whether it is necessary or not; the schematic is shown in Figure 3. In this paper, this mechanism is called retransmission mechanism in advance.
Diagram of data frame of advance retransmission mechanism in the process of transmission.
When retransmission frames are transmitted by master station in advance and number of retransmission is r, considering the above-mentioned minimum interval in the process of transmitting frames by master station, minimum of communication cycle is obtained as follows (unit is μs):
After using retransmission mechanism in advance, delay of communication cycle can be significantly reduced, which is caused by retransmitting frames. Take an example of the above-mentioned conditions.
(1) When datum from slave station is 8 bytes, number of slave station will be 24, by using single ring and Ethernet of 100 M, and number of retransmission is 1, transceiver time of each frame of master station is 39.36 μs, communication cycle is 78.72 μs, and transceiver time of retransmitting frames is also 39.36 μs. After using retransmission in advance, time is occupied by retransmission part for about 18.24 μs (15.36 μs + 2.88 μs), communication cycle will be 57.6 μs, and time will decrease to 26.8%.
(2) If by switching to use Ethernet of 1000 M the transceiver time of each frame is about 25.54 μs, the communication cycle which is added time-consuming is 51.07 μs. After using the retransmission in advance, time that is occupied by the part in retransmission is about 4.42 μs (1.54 μs + 2.88 μs), the communication cycle will be 29.95 μs, and the time will decrease to 41.2%.
As for using the Ethernet of 1000 M, from another point of view, After using retransmission mechanism, communication cycle (29.95 μs) is only more 4.42 μs than the same situation without using the retransmission mechanism, and extra parts account for 17.3%, that is to say, the increase in reliability can multiply be got at the cost of the increase 17.3% in communication cycle. Therefore, retransmission mechanism in advance is particularly suitable for utilization in large-scale and high-speed network.
4. Research on Reliability
Software mechanism of improving bus reliability is mainly about retransmission mechanism. The retransmission mechanism is a software mechanism, which has a low cost and advantages of high reliability, but the retransmission is at the expense of the reduction in communication cycle.
4.1. Contradiction of Reliability and Efficiency
For issues of minimum interval between data frames and frame leading, communication efficiency of bus can be effectively improved by using the lumped frame instead of multiple single-node frames, when the single-node data is less. When the interference is very frequent and the interference cycle is shorter than communication cycle of bus, the retransmission mechanism will lose its original significance.
The authors note that the existing different standards about data format of slave station is not specially designed for how to improve the reliability under the condition of retransmission, when the retransmission mechanism is used, thus relationship between the degree of improvement in reliability and number of retransmission is still not ideal. So an independent testing mechanism in data segments from lumped frame is proposed, and reliability in communication in the condition of retransmission can be significantly improved by using this mechanism.
4.2. Independent Verification of Data Segment
The system reliability can be improved by mechanism of independent verification of data segment from the perspective of reliability model, which can be proved as follows:
Figure 4 is a block diagram of reliability of parallel-serial system, whose mathematical model of reliability is shown as follows.
Block diagram of reliability in parallel and series system.
R ps is the reliability of the overall system, r ij is the reliability in the jth data segment from the ith intraframe, m is the number of communications, and n is number of slave stations. When the random interference and the length of the data segment from slave station are all the same, all of r ij are the same, and all of r ij values are set as r, and (5) can be simplified as follows:
The reliability of the system model can be described by using typical string and system; Figure 5 is a block diagram of reliability in series and parallel system, the mathematical model of reliability is shown as follows:
Block diagram of reliability in series and parallel system.
When random interferences and the lengths of the data segment from slave station are the same, all of r ij are the same, and all of r ij values are set as r, and (7) can be simplified as follows:
Considering general rule of the reliability, under the condition of the same in unit reliability, the reliability of series and parallel system is higher than the reliability of parallel and series system; therefore, reliability advantages of independent verification mechanism of data segment proposed by this paper can be proved.
In the process of specific implementation in independent verification mechanism of data segment, due to the need for adding parity data to the existing data segment, thus the overall efficiency of the bus transmission is decreased. When 16-bit CRC is used by verification of data segment, the example in this paper is comparatively analyzed as follows:
(1) When slave station data are 8 bytes, numbers of slave station are 24, and by using single ring and Ethernet of 100 M, two-byte CRC verification is added in data from each slave station; transceiver time for each frame of master station increases from 43.2 μs to 48 μs, communication cycle is 96 μs, and time is prolonged by 11.1%.
(2) If we change Ethernet of 1000 M to use without using retransmission in advance, transceiver time for each frame increases from 25.9 μs to 26.4 μs, communication cycle is 52.8 μs, and time is prolonged by 1.8%.
Something still needs to be noted in the process of specific implementation in independent verification mechanism of data segment; in the protocols such as EtherCAT, the data lengths of each slave station are stored within the data segment; when data are searched by slave station, it is needed to use this length to determine the position of next data segment.
4.3. Changing Mechanism of Data Segment Address
As for some extreme cases, interference cycle may be exactly the same with communication cycle; at the same time, whether segmented CRC verification mechanism is used by lumped frame or not may cause master station communicate with one or few slave stations.
As for this extreme case, sending frame time can be determined by characteristics of interference cycle which can be chosen by master station, except that reliability can be improved by autochange in position of data segment in lumped frames, which is called changing mechanism of data segment address in this paper.
Without using independent verification mechanism of data segment, no matter how to change position of data segment in intraframe, all of the data will be lost for the error of FCS in the all frames. By using independent verification mechanism of data segment, the data segment cannot rely on the FCS of entire frames and independently judges whether the data is correct or not; therefore, position change of data segment in frame can help some slave stations avoid interference so as to achieve the purpose of improvement in system reliability.
5. Verification Test and Design for Motion Control Bus
Firstly, this section has designed a set of basic communication protocol in motion control bus the optimization mechanism proposed in this paper is used in the protocol, and then we have used verification platform to achieve this protocol and proved effectiveness of the mechanism proposed in the paper by the actual operation and reliability verification.
5.1. Low-Level Protocol in Bus
In order to verify the optimization mechanism proposed in this paper for motion control bus, a set of basic protocol based on 100 M Ethernet physical layer for motion control bus was designed and implemented in the paper. Frame format of the protocol is shown in Figure 6, and the corresponding field is described in Table 1.
Description for frame format of motion control bus.
Frame format of motion control bus.
Realization principle for independent verification mechanism of data segment is shown as follows: Sn_LENGTH defines the length of the data segment of the nth slave, slave station x can determines the location of its own data segment according to accumulated values from S1_LENGTH to S (x – 1)_LENGTH, both INDEXLENGTH and INDEX from index segments have verification ICS to can ensure the reliability of the index. Precondition for realizing mechanism of the arrival prediction is shown as follows: the protocol in this paper requires frames timely sent for master station to be transmission interval is sent to slave station through data segment of slave station after completion of initialization for address of slave station. To simplify the design, the protocol requires that a frame can be considered to receive after only detecting correct ICS. The retransmission mechanism in advance is relatively simple to achieve. In order to ensure normal work for the arrival of prediction mechanism and address allocation mechanism, rule is provided as follows: when address reset frames and data transmission frames are sent, function on retransmission and retransmission in advance can be used, while function on retransmission and retransmission in advance cannot be used in the process of allocating address.
5.2. Design and Realization of FPGA for Master Station and Slave Station
According to the protocol defined in this paper, function of FPGA from master station is relatively simple, and block diagram of the master station is shown in Figure 7.
Block diagram of the master station.
Because the slave station needs to achieve straight-through forwarding function and generation function of synchronization signal, the slave function is relatively complex; block diagram of slave station is shown in Figure 8. The pass-through forwarding principle simultaneously receives and transmits, so receiving module of slave station and sending module of slave station are tightly coupled. Both of them link each other through sending strobe module shown in Figure 8.
Block diagram of the slave station.
5.3. The Overall Operation of the System and Reliability Verification
In order to verify the correctness of this protocol in this paper and design of FPGA of master and slave stations, this paper achieves protocol from Section 5.1 in system hardware platform. The configuration of hardware and software is set as follows.
The master station and slave station use embedded motion controller body; software is based on operating system of μC/OS2.
The slave station uses slave station verification board.
Test system has 8 slave stations; when we use a single ring structure, the number of retransmission is 1. In order to verify the mechanism proposed in this paper in different working environments, the amount of data from slave station is used as standard; test conditions are divided into two groups, which are shown in Table 2.
Test system for the bus parameters.
Figure 9 (a) is a debugging and synchronization performance testing, field environment of reliability testing. From Figure 9 (b), synchronous jitter of the eight slave station is within 160 ns. Local clock of testing platform is 50 MHz, so results are in line with theoretical and simulation analysis from Section 2.2 in this paper.
Synchronization performance and reliability testing site and synchronization waveform.
In order to verify the performance of independent verification mechanism of the data segment, this paper uses a burst interference device SKS-0404 and static equipment SKS-0230 to simulate power supply and electromagnetic interference in the actual industrial environment so as to increase the interference effect.
The reliability data is uploaded to PC for analysis by the master station through serials; successful communication criteria are defined as follows: (1) index segment verification ICS is correct; (2) Among the starting frame and the retransmission frame, one of the SCS came form data segment of all the slave stations is correct at random, and datum of the CMD/STA domain came from data segment are in line with the pre-specified format at the same time.
The test time was one hour, and test results are shown in Table 3. When we do not use independent verification of the data segment, two frames FCS are wrong, so it is considered that the communication is a failure, and the number in Group A test is 58; if the independent verification of data segment is used, the number of actual communication failure is 18 times; reliability has significantly improved. From the analysis of data communication failure, we can find that, in group A test ICS error, that is, parity error of index segments reaches 15, and index segment of independent verification mechanism of the data segment is communication failure factors, this situation is also consistent with the theoretical analysis. To work out this weak link, in some special networks, this paper proposes to use a protocol whose data segment has fixed length, and there is no need to use index segment in this circumstance, so salve station can directly find data segment by their own address, that is to say, reliability can be further improved.
Testing results for reliability of motion control bus.
From the comparison of the results of Group A and Group B, when the test time is the same, with the increase in the amount of the node data, the error probability is also increased, but increasing speed for error will be different if the mechanism proposed in this paper is used. The chance of error increases from the extreme of 0.0054 to 0.0172 with an increase of 319% when we do not use this mechanism. But by using the mechanism in this paper, the chance of error increases from the extreme of 0.0012 to 0.0022 with an increase of 183%, which illustrates that improvement effect for large datum transmission will be more obvious in this paper. Analysis from above-mentioned ICS error shows that the ICS error is the main cause of communication failure; when the amount of data increases, the ICS error ratio decreases from 83.3% to 58.3%, which indicates that the mechanism in this paper has better performance when large amount of datum is transmitted.
6. Conclusions
In summary, this paper proposes the prediction mechanism in the arrival of the frames, the retransmission mechanism in advance, and a new independent verification of data segment. Tests show that the mechanism in this paper has better performance when large amount of datum is transmitted, and it is suitable for control system to transmit data.
Footnotes
Acknowledgment
This work is funded by the major projects of the National Science and Technology 04 special project: algorithm in whole digital and high-grade numerical control device and research on numerical control system field bus.