Abstract
Introduction
Physical attacks can bypass cryptographic algorithms or protocols and get the sensitive data in memory directly, if they are stored in plaintext.
Several secure processor architectures are proposed which provide both memory confidentiality and integrity. We propose a novel architecture for an embedded system to provide efficient memory protection.
Main Method
CPU or SoC in the embedded system is considered the “trusted root,” and all the other components are unauthentic. Secure engine (SE) is a component in CPU or SoC, whose duty is to provide data encryption and authentication when they go through SE.
A novel and efficient SE is proposed in this abstract. It adopts OTP encryption and GCM as working mode when processing cryptographic issues. Each block is assigned a counter which is stored in memory. When the block is replaced out from the cache, its counter is added 1. For example, the ith block is indicated as blocki and its counter counteri. Blocki is divided into for sub-blocks. Using this counter, each block generates a unique seed as address‖counter‖EIV. By this seed, SE computes pad as Ekey(address‖counter‖EIV), where “key” indicates the system key which is a system-wide secret. Then, GCM mode will simultaneously output the encrypted block and its MAC. These methods will help to vault the system performance greatly, according to our simulation.
Besides the basic architecture, we propose a counter cache structure to SE and an accelerated MAC verification to enhance the system efficiency. Counter cache adopts the locality feature of memory to expedite counter reading. The accelerated MAC helps each block to store its corresponding MAC value in a parallel MAC memory which hides MAC read latency by overlapping by main memory latency.
Performance Evaluation
We simulate the architecture based on the SimpleScalar tool set with six SPEC2000 benchmarks. The simulation results of our system show benign performance which outperforms AEGIS by 33% averagely.